URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [udiv.cgs] - Rev 24
Go to most recent revision | Compare with Previous | Blame | View Log
# frv testcase for udiv $GRi,$GRj,$GRk
# mach: fr400
.include "../testutils.inc"
start
.global udiv
udiv:
; simple division 12 / 3
set_gr_immed 0x00000003,gr2
set_gr_immed 0x0000000c,gr3
udiv gr3,gr2,gr3
test_gr_immed 0x00000003,gr2
test_gr_immed 0x00000004,gr3
; example 1 from udiv in the fr30 manual
set_gr_limmed 0x0123,0x4567,gr2
set_gr_limmed 0xfedc,0xba98,gr3
udiv gr3,gr2,gr3
test_gr_limmed 0x0123,0x4567,gr2
test_gr_immed 0x000000e0,gr3
; set up exception handler
set_psr_et 1
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x170,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_gr_immed 0,gr15
; divide by zero
set_spr_addr ok1,lr
e1: udiv gr1,gr0,gr2 ; divide by zero
test_gr_immed 1,gr15
pass
ok1: ; exception handler for divide by zero
test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
inc_gr_immed 1,gr15
rett 0
fail
Go to most recent revision | Compare with Previous | Blame | View Log