OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [cmpu.cgs] - Rev 816

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for cmpu $src1,$src2
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global cmpu
cmpu:
        mvi_h_condbit 0
        mvi_h_gr r4, 1
        mvi_h_gr r5, -2
        cmpu r4, r5
        bc ok
not_ok:
        fail
ok:
        mvi_h_condbit 1
        mvi_h_gr r4, -1
        cmpu r4, r5
        bc not_ok

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.