OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [mvtachi.cgs] - Rev 24

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for mvtachi $src1
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global mvtachi
mvtachi:
        mvi_h_accum0 0, 0

        mvi_h_gr r4, 0x11223344
        mvtachi r4
        test_h_accum0 0x223344, 0x0

        mvi_h_gr r4, 0x99aabbcc
        mvtachi r4
        test_h_accum0 0xffaabbcc, 0x0

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.