OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [misc/] [fr-dr.s] - Rev 853

Go to most recent revision | Compare with Previous | Blame | View Log

# sh testcase for floating point register shared state (see below).
# mach: all
# as: -isa=shmedia
# ld: -m shelf64
 
# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state).
# Hitachi SH-5 CPU volume 1, p. 15.
 
	.include "media/testutils.inc"
 
	start
 
	movi 42, r0
	fmov.ls r0, fr12
	# save this reg.
	fmov.s fr12, fr14
 
	movi 42, r0
	fmov.qd r0, dr12
 
okay:
	pass
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.