OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [common/] [gdbinit.in] - Rev 842

Compare with Previous | Blame | View Log

break sim_io_error
break sim_core_signal
@cgen_breaks@

define dump
set sim_debug_dump ()
end

document dump
Dump cpu and simulator registers for debugging the simulator.
Requires the simulator to provide function sim_debug_dump.
end

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.