URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [mips/] [tx.igen] - Rev 842
Compare with Previous | Blame | View Log
// -*- C -*-//// toshiba specific instructions.//011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD"madd r<RS>, r<RT>":RD == 0"madd r<RD>, r<RS>, r<RT>"*r3900{signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))+ ((signed64) EXTEND32 (GPR[RT])* (signed64) EXTEND32 (GPR[RS])));check_mult_hilo (SD_, HIHISTORY, LOHISTORY);TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);LO = EXTEND32 (prod);HI = EXTEND32 (VH4_8 (prod));TRACE_ALU_RESULT2 (HI, LO);if(RD != 0 )GPR[RD] = LO;}011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU"maddu r<RS>, r<RT>":RD == 0"maddu r<RD>, r<RS>, r<RT>"*r3900{unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))+ ((unsigned64) VL4_8 (GPR[RS])* (unsigned64) VL4_8 (GPR[RT])));check_mult_hilo (SD_, HIHISTORY, LOHISTORY);TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);LO = EXTEND32 (prod);HI = EXTEND32 (VH4_8 (prod));TRACE_ALU_RESULT2 (HI, LO);if(RD != 0)GPR[RD] = LO;}000000,CODE.20,001110::CO1:::SDBBP"sdbbp"*r3900:{SignalException (DebugBreakPoint, instruction);}
