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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [bchilr.cgs] - Rev 842
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# frv testcase for bchilr $ICCi,$ccond,$hint# mach: all.include "testutils.inc"start.global bchilrbchilr:; ccond is trueset_spr_immed 128,lcrset_spr_addr ok1,lrset_icc 0x0 0bchilr icc0,0,0failok1:set_spr_addr bad,lrset_icc 0x1 1bchilr icc1,0,1set_spr_addr ok3,lrset_icc 0x2 2bchilr icc2,0,2failok3:set_spr_addr bad,lrset_icc 0x3 3bchilr icc3,0,3set_spr_addr bad,lrset_icc 0x4 0bchilr icc0,0,0set_spr_addr bad,lrset_icc 0x5 1bchilr icc1,0,1set_spr_addr bad,lrset_icc 0x6 2bchilr icc2,0,2set_spr_addr bad,lrset_icc 0x7 3bchilr icc3,0,3set_spr_addr ok9,lrset_icc 0x8 0bchilr icc0,0,0failok9:set_spr_addr bad,lrset_icc 0x9 1bchilr icc1,0,1set_spr_addr okb,lrset_icc 0xa 2bchilr icc2,0,2failokb:set_spr_addr bad,lrset_icc 0xb 3bchilr icc3,0,3set_spr_addr bad,lrset_icc 0xc 0bchilr icc0,0,0set_spr_addr bad,lrset_icc 0xd 1bchilr icc1,0,1set_spr_addr bad,lrset_icc 0xe 2bchilr icc2,0,2set_spr_addr bad,lrset_icc 0xf 3bchilr icc3,0,3; ccond is trueset_spr_immed 1,lcrset_spr_addr okh,lrset_icc 0x0 0bchilr icc0,1,0failokh:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x1 1bchilr icc1,1,1set_spr_immed 1,lcrset_spr_addr okj,lrset_icc 0x2 2bchilr icc2,1,2failokj:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x3 3bchilr icc3,1,3set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x4 0bchilr icc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x5 1bchilr icc1,1,1set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x6 2bchilr icc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x7 3bchilr icc3,1,3set_spr_immed 1,lcrset_spr_addr okp,lrset_icc 0x8 0bchilr icc0,1,0failokp:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x9 1bchilr icc1,1,1set_spr_immed 1,lcrset_spr_addr okr,lrset_icc 0xa 2bchilr icc2,1,2failokr:set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xb 3bchilr icc3,1,3set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xc 0bchilr icc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xd 1bchilr icc1,1,1set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xe 2bchilr icc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0xf 3bchilr icc3,1,3; ccond is falseset_spr_immed 128,lcrset_spr_addr bad,lrset_icc 0x0 0bchilr icc0,1,0set_icc 0x1 1bchilr icc1,1,1set_icc 0x2 2bchilr icc2,1,2set_icc 0x3 3bchilr icc3,1,3set_icc 0x4 0bchilr icc0,1,0set_icc 0x5 1bchilr icc1,1,1set_icc 0x6 2bchilr icc2,1,2set_icc 0x7 3bchilr icc3,1,3set_icc 0x8 0bchilr icc0,1,0set_icc 0x9 1bchilr icc1,1,1set_icc 0xa 2bchilr icc2,1,2set_icc 0xb 3bchilr icc3,1,3set_icc 0xc 0bchilr icc0,1,0set_icc 0xd 1bchilr icc1,1,1set_icc 0xe 2bchilr icc2,1,2set_icc 0xf 3bchilr icc3,1,3; ccond is falseset_spr_immed 1,lcrset_spr_addr bad,lrset_icc 0x0 0bchilr icc0,0,0set_spr_immed 1,lcrset_icc 0x1 1bchilr icc1,0,1set_spr_immed 1,lcrset_icc 0x2 2bchilr icc2,0,2set_spr_immed 1,lcrset_icc 0x3 3bchilr icc3,0,3set_spr_immed 1,lcrset_icc 0x4 0bchilr icc0,0,0set_spr_immed 1,lcrset_icc 0x5 1bchilr icc1,0,1set_spr_immed 1,lcrset_icc 0x6 2bchilr icc2,0,2set_spr_immed 1,lcrset_icc 0x7 3bchilr icc3,0,3set_spr_immed 1,lcrset_icc 0x8 0bchilr icc0,0,0set_spr_immed 1,lcrset_icc 0x9 1bchilr icc1,0,1set_spr_immed 1,lcrset_icc 0xa 2bchilr icc2,0,2set_spr_immed 1,lcrset_icc 0xb 3bchilr icc3,0,3set_spr_immed 1,lcrset_icc 0xc 0bchilr icc0,0,0set_spr_immed 1,lcrset_icc 0xd 1bchilr icc1,0,1set_spr_immed 1,lcrset_icc 0xe 2bchilr icc2,0,2set_spr_immed 1,lcrset_icc 0xf 3bchilr icc3,0,3passbad:fail