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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [fr550/] [cmqmachu.cgs] - Rev 834
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# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond# mach: all.include "../testutils.inc"start.global cmqmachucmqmachu:set_spr_immed 0x1b1b,cccrset_spr_immed 0,msr0set_accg_immed 0,accg0set_acc_immed 0,acc0set_accg_immed 0,accg1set_acc_immed 0,acc1set_accg_immed 0,accg2set_acc_immed 0,acc2set_accg_immed 0,accg3set_acc_immed 0,acc3set_fr_iimmed 3,2,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 1,2,fr9 ; multiply by 1set_fr_iimmed 2,1,fr11cmqmachu fr8,fr10,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1test_accg_immed 0,accg2test_acc_immed 2,acc2test_accg_immed 0,accg3test_acc_immed 2,acc3set_fr_iimmed 0,2,fr8 ; multiply by 0set_fr_iimmed 2,0,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11cmqmachu fr8,fr10,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1test_accg_immed 0,accg2test_acc_limmed 0x0000,0x8000,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x8000,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x8000,2,fr9 ; 17 bit resultset_fr_iimmed 2,0x8000,fr11cmqmachu fr8,fr10,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8006,acc1test_accg_immed 0,accg2test_acc_immed 0x00018000,acc2test_accg_immed 0,accg3test_acc_immed 0x00018000,acc3set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11cmqmachu fr8,fr10,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 0x3fff8007,acc0test_accg_immed 0,accg1test_acc_immed 0x3fff8007,acc1test_accg_immed 0,accg2test_acc_limmed 0x4001,0x8000,acc2test_accg_immed 0,accg3test_acc_limmed 0x4001,0x8000,acc3set_fr_iimmed 0xffff,0xffff,fr8 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0xffff,0xffff,fr9 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 1,accg0test_acc_limmed 0x3ffd,0x8008,acc0test_accg_immed 1,accg1test_acc_limmed 0x3ffd,0x8008,acc1test_accg_immed 1,accg2test_acc_limmed 0x3fff,0x8001,acc2test_accg_immed 1,accg3test_acc_limmed 0x3fff,0x8001,acc3set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0xff,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 1,1,fr9set_fr_iimmed 1,1,fr11cmqmachu fr8,fr10,acc0,cc4,1test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1test_accg_immed 0xff,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0xff,accg3test_acc_limmed 0xffff,0xffff,acc3set_fr_iimmed 0xffff,0x0000,fr8set_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0x0000,0xffff,fr9set_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc4,1test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1test_accg_immed 0xff,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0xff,accg3test_acc_limmed 0xffff,0xffff,acc3set_spr_immed 0,msr0set_accg_immed 0,accg0set_acc_immed 0,acc0set_accg_immed 0,accg1set_acc_immed 0,acc1set_accg_immed 0,accg2set_acc_immed 0,acc2set_accg_immed 0,accg3set_acc_immed 0,acc3set_fr_iimmed 3,2,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 1,2,fr9 ; multiply by 1set_fr_iimmed 2,1,fr11cmqmachu fr8,fr10,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1test_accg_immed 0,accg2test_acc_immed 2,acc2test_accg_immed 0,accg3test_acc_immed 2,acc3set_fr_iimmed 0,2,fr8 ; multiply by 0set_fr_iimmed 2,0,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11cmqmachu fr8,fr10,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1test_accg_immed 0,accg2test_acc_limmed 0x0000,0x8000,acc2test_accg_immed 0,accg3test_acc_limmed 0x0000,0x8000,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x8000,2,fr9 ; 17 bit resultset_fr_iimmed 2,0x8000,fr11cmqmachu fr8,fr10,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8006,acc1test_accg_immed 0,accg2test_acc_immed 0x00018000,acc2test_accg_immed 0,accg3test_acc_immed 0x00018000,acc3set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11cmqmachu fr8,fr10,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0,accg0test_acc_immed 0x3fff8007,acc0test_accg_immed 0,accg1test_acc_immed 0x3fff8007,acc1test_accg_immed 0,accg2test_acc_limmed 0x4001,0x8000,acc2test_accg_immed 0,accg3test_acc_limmed 0x4001,0x8000,acc3set_fr_iimmed 0xffff,0xffff,fr8 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0xffff,0xffff,fr9 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 1,accg0test_acc_limmed 0x3ffd,0x8008,acc0test_accg_immed 1,accg1test_acc_limmed 0x3ffd,0x8008,acc1test_accg_immed 1,accg2test_acc_limmed 0x3fff,0x8001,acc2test_accg_immed 1,accg3test_acc_limmed 0x3fff,0x8001,acc3set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0xff,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 1,1,fr9set_fr_iimmed 1,1,fr11cmqmachu fr8,fr10,acc0,cc5,0test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1test_accg_immed 0xff,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0xff,accg3test_acc_limmed 0xffff,0xffff,acc3set_fr_iimmed 0xffff,0x0000,fr8set_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0x0000,0xffff,fr9set_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc5,0test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xffff,acc1test_accg_immed 0xff,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0xff,accg3test_acc_limmed 0xffff,0xffff,acc3set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_accg_immed 0x00000033,accg2set_acc_immed 0x33333333,acc2set_accg_immed 0x00000044,accg3set_acc_immed 0x44444444,acc3set_fr_iimmed 3,2,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 1,2,fr9 ; multiply by 1set_fr_iimmed 2,1,fr11cmqmachu fr8,fr10,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0,2,fr8 ; multiply by 0set_fr_iimmed 2,0,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11cmqmachu fr8,fr10,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x8000,2,fr9 ; 17 bit resultset_fr_iimmed 2,0x8000,fr11cmqmachu fr8,fr10,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11cmqmachu fr8,fr10,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0xffff,0xffff,fr8 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0xffff,0xffff,fr9 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0xff,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 1,1,fr9set_fr_iimmed 1,1,fr11cmqmachu fr8,fr10,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3set_fr_iimmed 0xffff,0x0000,fr8set_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0x0000,0xffff,fr9set_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_accg_immed 0x00000033,accg2set_acc_immed 0x33333333,acc2set_accg_immed 0x00000044,accg3set_acc_immed 0x44444444,acc3set_fr_iimmed 3,2,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 1,2,fr9 ; multiply by 1set_fr_iimmed 2,1,fr11cmqmachu fr8,fr10,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0,2,fr8 ; multiply by 0set_fr_iimmed 2,0,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11cmqmachu fr8,fr10,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x8000,2,fr9 ; 17 bit resultset_fr_iimmed 2,0x8000,fr11cmqmachu fr8,fr10,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11cmqmachu fr8,fr10,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0xffff,0xffff,fr8 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0xffff,0xffff,fr9 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0xff,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 1,1,fr9set_fr_iimmed 1,1,fr11cmqmachu fr8,fr10,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3set_fr_iimmed 0xffff,0x0000,fr8set_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0x0000,0xffff,fr9set_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_accg_immed 0x00000033,accg2set_acc_immed 0x33333333,acc2set_accg_immed 0x00000044,accg3set_acc_immed 0x44444444,acc3set_fr_iimmed 3,2,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 1,2,fr9 ; multiply by 1set_fr_iimmed 2,1,fr11cmqmachu fr8,fr10,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0,2,fr8 ; multiply by 0set_fr_iimmed 2,0,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11cmqmachu fr8,fr10,acc0,cc2,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x8000,2,fr9 ; 17 bit resultset_fr_iimmed 2,0x8000,fr11cmqmachu fr8,fr10,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11cmqmachu fr8,fr10,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0xffff,0xffff,fr8 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0xffff,0xffff,fr9 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0xff,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 1,1,fr9set_fr_iimmed 1,1,fr11cmqmachu fr8,fr10,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3set_fr_iimmed 0xffff,0x0000,fr8set_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0x0000,0xffff,fr9set_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3;set_spr_immed 0,msr0set_accg_immed 0x00000011,accg0set_acc_immed 0x11111111,acc0set_accg_immed 0x00000022,accg1set_acc_immed 0x22222222,acc1set_accg_immed 0x00000033,accg2set_acc_immed 0x33333333,acc2set_accg_immed 0x00000044,accg3set_acc_immed 0x44444444,acc3set_fr_iimmed 3,2,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 1,2,fr9 ; multiply by 1set_fr_iimmed 2,1,fr11cmqmachu fr8,fr10,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0,2,fr8 ; multiply by 0set_fr_iimmed 2,0,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr11cmqmachu fr8,fr10,acc0,cc3,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 2,0x4000,fr10set_fr_iimmed 0x8000,2,fr9 ; 17 bit resultset_fr_iimmed 2,0x8000,fr11cmqmachu fr8,fr10,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11cmqmachu fr8,fr10,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_fr_iimmed 0xffff,0xffff,fr8 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0xffff,0xffff,fr9 ; max positive resultset_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0x00000011,accg0test_acc_immed 0x11111111,acc0test_accg_immed 0x00000022,accg1test_acc_immed 0x22222222,acc1test_accg_immed 0x00000033,accg2test_acc_immed 0x33333333,acc2test_accg_immed 0x00000044,accg3test_acc_immed 0x44444444,acc3set_accg_immed 0xff,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0xff,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0xff,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0xff,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 1,1,fr9set_fr_iimmed 1,1,fr11cmqmachu fr8,fr10,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3set_fr_iimmed 0xffff,0x0000,fr8set_fr_iimmed 0xffff,0xffff,fr10set_fr_iimmed 0x0000,0xffff,fr9set_fr_iimmed 0xffff,0xffff,fr11cmqmachu fr8,fr10,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always settest_accg_immed 0xff,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0xff,accg1test_acc_immed 0xffffffff,acc1test_accg_immed 0xff,accg2 ; saturationtest_acc_immed 0xffffffff,acc2test_accg_immed 0xff,accg3test_acc_immed 0xffffffff,acc3pass
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