OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [lduh.cgs] - Rev 828

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for lduh $dr,@$sr
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global lduh
lduh:
        mvaddr_h_gr r4, data_loc
        mvi_h_gr    r5, 0

        lduh r5, @r4

        test_h_gr r5, 0x8010 ; big endian processor

        pass

data_loc:
        .word 0x8010f020

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.