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# v850 div
# mach: v850e
# as(v850e): -mv850e

        .include "testutils.inc"

# Regular division - check signs
# The S flag is based on the quotient, not the remainder

        seti    6, r1
        seti    45, r2
        div     r1, r2, r3

        flags   0
        reg     r1, 6
        reg     r2, 7
        reg     r3, 3

        seti    -6, r1
        seti    45, r2
        div     r1, r2, r3

        flags   s
        reg     r1, -6
        reg     r2, -7
        reg     r3, 3

        seti    6, r1
        seti    -45, r2
        div     r1, r2, r3

        flags   s
        reg     r1, 6
        reg     r2, -7
        reg     r3, -3

        seti    -6, r1
        seti    -45, r2
        div     r1, r2, r3

        flags   0
        reg     r1, -6
        reg     r2, 7
        reg     r3, -3

# If the data is divided by zero, OV=1 and the quotient is undefined.
# According to NEC, the S and Z flags, and the output registers, are
# unchanged.

        noflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        div     r1, r2, r3

        flags   v
        reg     r2, 45
        reg     r3, 67

        allflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        div     r1, r2, r3

        flags   sat + c + v + s + z
        reg     r2, 45
        reg     r3, 67

# Zero / (N!=0) => normal

        noflags
        seti    45, r1
        seti    0, r2
        seti    67, r3
        div     r1, r2, r3

        flags   z
        reg     r1, 45
        reg     r2, 0
        reg     r3, 0

# Test for regular overflow

        noflags
        seti    -1, r1
        seti    0x80000000, r2
        seti    67, r3
        div     r1, r2, r3

        flags   v + s
        reg     r1, -1
        reg     r2, 0x80000000
        reg     r3, 0

# The Z flag is based on the quotient, not the remainder

        noflags
        seti    45, r1
        seti    16, r2
        div     r1, r2, r3

        flags   z
        reg     r2, 0
        reg     r3, 16

# If the quot and rem registers are the same, the remainder is stored.

        seti    6, r1
        seti    45, r2
        div     r1, r2, r2

        flags   0
        reg     r1, 6
        reg     r2, 3


        pass