URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [v850/] [shl.cgs] - Rev 842
Compare with Previous | Blame | View Log
# v850 shl
# mach: all
.include "testutils.inc"
# CY is set to 1 if the bit shifted out last is 1, else 0
# OV is set to zero.
# Z is set if the result is 0, else 0
noflags
seti 1, r1
seti 0x00000000, r2
shl r1, r2
flags z
reg r2, 0
noflags
seti 1, r1
seti 0x80000000, r2
shl r1, r2
flags c + z
reg r2, 0
noflags
seti 0x00000000, r2
shl 1, r2
flags z
reg r2, 0
noflags
seti 0x80000000, r2
shl 1, r2
flags c + z
reg r2, 0
# However, if the number of shifts is 0, CY is 0.
noflags
seti 0, r1
seti 0xffffffff, r2
shl r1, r2
flags s
reg r2, 0xffffffff
noflags
seti 0xffffffff, r2
shl 0, r2
flags s
reg r2, 0xffffffff
# Zero is shifted into the LSB
# S is 1 if the result is negative, else 0
noflags
seti 1, r1
seti 0x4000000f, r2
shl r1, r2
flags s
reg r2, 0x8000001e
noflags
seti 0x4000000f, r2
shl 1, r2
flags s
reg r2, 0x8000001e
pass