URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [i386/] [x86-64-mem.d] - Rev 448
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#as: -J
#objdump: -dw
#name: x86-64 mem
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f 01 06 sgdt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 0e sidt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 16 lgdt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 1e lidt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 3e invlpg \(%rsi\)
[ ]*[a-f0-9]+: 0f c7 0e cmpxchg8b \(%rsi\)
[ ]*[a-f0-9]+: 48 0f c7 0e cmpxchg16b \(%rsi\)
[ ]*[a-f0-9]+: 0f c7 36 vmptrld \(%rsi\)
[ ]*[a-f0-9]+: 66 0f c7 36 vmclear \(%rsi\)
[ ]*[a-f0-9]+: f3 0f c7 36 vmxon \(%rsi\)
[ ]*[a-f0-9]+: 0f c7 3e vmptrst \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 06 fxsave \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 0e fxrstor \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 16 ldmxcsr \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 1e stmxcsr \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 3e clflush \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 06 sgdt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 0e sidt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 16 lgdt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 1e lidt \(%rsi\)
[ ]*[a-f0-9]+: 0f 01 3e invlpg \(%rsi\)
[ ]*[a-f0-9]+: 0f c7 0e cmpxchg8b \(%rsi\)
[ ]*[a-f0-9]+: 48 0f c7 0e cmpxchg16b \(%rsi\)
[ ]*[a-f0-9]+: 0f c7 36 vmptrld \(%rsi\)
[ ]*[a-f0-9]+: 66 0f c7 36 vmclear \(%rsi\)
[ ]*[a-f0-9]+: f3 0f c7 36 vmxon \(%rsi\)
[ ]*[a-f0-9]+: 0f c7 3e vmptrst \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 06 fxsave \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 0e fxrstor \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 16 ldmxcsr \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 1e stmxcsr \(%rsi\)
[ ]*[a-f0-9]+: 0f ae 3e clflush \(%rsi\)
#pass
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