OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [iq2000/] [yield1.s] - Rev 156

Compare with Previous | Blame | View Log

# This test case includes a single case of a yield instruction
# (e.g. SLEEP) appearing in the branch delay slot.  We expect
# the assembler to issue a warning about this!
 
.text
	jalr %3, %4
	# sleep insn in the branch delay slot.
	sleep
foo:	nop

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.