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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [sparc/] [splet.d] - Rev 156
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#as: -Asparclet#objdump: -dr#name: sparclet extensions.*: +file format .*Disassembly of section .text:0+ <start>:0: a1 40 00 00 rd %y, %l04: a1 40 40 00 rd %asr1, %l08: a1 43 c0 00 rd %asr15, %l0c: a1 44 40 00 rd %asr17, %l010: a1 44 80 00 rd %asr18, %l014: a1 44 c0 00 rd %asr19, %l018: a1 45 00 00 rd %asr20, %l01c: a1 45 40 00 rd %asr21, %l020: a1 45 80 00 rd %asr22, %l024: 81 84 20 00 mov %l0, %y28: 83 84 20 00 mov %l0, %asr12c: 9f 84 20 00 mov %l0, %asr1530: a3 84 20 00 mov %l0, %asr1734: a5 84 20 00 mov %l0, %asr1838: a7 84 20 00 mov %l0, %asr193c: a9 84 20 00 mov %l0, %asr2040: ab 84 20 00 mov %l0, %asr2144: ad 84 20 00 mov %l0, %asr220+48 <test_umul>:48: 86 50 40 02 umul %g1, %g2, %g34c: 86 50 40 02 umul %g1, %g2, %g30+50 <test_smul>:50: 86 58 40 02 smul %g1, %g2, %g354: 86 58 40 02 smul %g1, %g2, %g30+58 <test_stbar>:58: 81 43 c0 00 stbar5c: 81 43 c0 00 stbar60: 00 00 00 01 unimp 0x164: 81 dc 40 00 flush %l10+68 <test_scan>:68: a7 64 7f ff scan %l1, -1, %l36c: a7 64 60 00 scan %l1, 0, %l370: a7 64 40 11 scan %l1, %l1, %l30+74 <test_shuffle>:74: a3 6c 20 01 shuffle %l0, 1, %l178: a3 6c 20 02 shuffle %l0, 2, %l17c: a3 6c 20 04 shuffle %l0, 4, %l180: a3 6c 20 08 shuffle %l0, 8, %l184: a3 6c 20 10 shuffle %l0, 0x10, %l188: a3 6c 20 18 shuffle %l0, 0x18, %l10+8c <test_umac>:8c: a1 f4 40 12 umac %l1, %l2, %l090: a1 f4 60 02 umac %l1, 2, %l094: a1 f4 60 02 umac %l1, 2, %l00+98 <test_umacd>:98: a1 74 80 14 umacd %l2, %l4, %l09c: a1 74 a0 03 umacd %l2, 3, %l0a0: a1 74 a0 03 umacd %l2, 3, %l00+a4 <test_smac>:a4: a1 fc 40 12 smac %l1, %l2, %l0a8: a1 fc 7f d6 smac %l1, -42, %l0ac: a1 fc 7f d6 smac %l1, -42, %l00+b0 <test_smacd>:b0: a1 7c 80 14 smacd %l2, %l4, %l0b4: a1 7c a0 7b smacd %l2, 0x7b, %l0b8: a1 7c a0 7b smacd %l2, 0x7b, %l00+bc <test_umuld>:bc: 90 4a 80 0c umuld %o2, %o4, %o0c0: 90 4a a2 34 umuld %o2, 0x234, %o0c4: 90 4a a5 67 umuld %o2, 0x567, %o00+c8 <test_smuld>:c8: b0 6e 80 1c smuld %i2, %i4, %i0cc: b0 6e b0 00 smuld %i2, -4096, %i0d0: b0 6f 2f ff smuld %i4, 0xfff, %i00+d4 <test_coprocessor>:d4: 81 b4 00 11 cpush %l0, %l1d8: 81 b4 20 01 cpush %l0, 1dc: 81 b4 00 51 cpusha %l0, %l1e0: 81 b4 20 41 cpusha %l0, 1e4: a1 b0 00 80 cpull %l0e8: a1 b0 01 00 crdcxt %ccsr, %l0ec: a1 b0 41 00 crdcxt %ccfr, %l0f0: a1 b0 c1 00 crdcxt %ccpr, %l0f4: a1 b0 81 00 crdcxt %cccrcr, %l0f8: 81 b4 00 c0 cwrcxt %l0, %ccsrfc: 83 b4 00 c0 cwrcxt %l0, %ccfr100: 87 b4 00 c0 cwrcxt %l0, %ccpr104: 85 b4 00 c0 cwrcxt %l0, %cccrcr108: 01 c0 00 01 cbn 10c <test_coprocessor\+(0x|)38>108: WDISP22 stop\+0xfffffef810c: 01 00 00 00 nop110: 21 c0 00 01 cbn,a 114 <test_coprocessor\+(0x|)40>110: WDISP22 stop\+0xfffffef0114: 01 00 00 00 nop118: 03 c0 00 01 cbe 11c <test_coprocessor\+(0x|)48>118: WDISP22 stop\+0xfffffee811c: 01 00 00 00 nop120: 23 c0 00 01 cbe,a 124 <test_coprocessor\+(0x|)50>120: WDISP22 stop\+0xfffffee0124: 01 00 00 00 nop128: 05 c0 00 01 cbf 12c <test_coprocessor\+(0x|)58>128: WDISP22 stop\+0xfffffed812c: 01 00 00 00 nop130: 25 c0 00 01 cbf,a 134 <test_coprocessor\+(0x|)60>130: WDISP22 stop\+0xfffffed0134: 01 00 00 00 nop138: 07 c0 00 01 cbef 13c <test_coprocessor\+(0x|)68>138: WDISP22 stop\+0xfffffec813c: 01 00 00 00 nop140: 27 c0 00 01 cbef,a 144 <test_coprocessor\+(0x|)70>140: WDISP22 stop\+0xfffffec0144: 01 00 00 00 nop148: 09 c0 00 01 cbr 14c <test_coprocessor\+(0x|)78>148: WDISP22 stop\+0xfffffeb814c: 01 00 00 00 nop150: 29 c0 00 01 cbr,a 154 <test_coprocessor\+(0x|)80>150: WDISP22 stop\+0xfffffeb0154: 01 00 00 00 nop158: 0b c0 00 01 cber 15c <test_coprocessor\+(0x|)88>158: WDISP22 stop\+0xfffffea815c: 01 00 00 00 nop160: 2b c0 00 01 cber,a 164 <test_coprocessor\+(0x|)90>160: WDISP22 stop\+0xfffffea0164: 01 00 00 00 nop168: 0d c0 00 01 cbfr 16c <test_coprocessor\+(0x|)98>168: WDISP22 stop\+0xfffffe9816c: 01 00 00 00 nop170: 2d c0 00 01 cbfr,a 174 <test_coprocessor\+(0x|)a0>170: WDISP22 stop\+0xfffffe90174: 01 00 00 00 nop178: 0f c0 00 01 cbefr 17c <test_coprocessor\+(0x|)a8>178: WDISP22 stop\+0xfffffe8817c: 01 00 00 00 nop180: 2f c0 00 01 cbefr,a 184 <test_coprocessor\+(0x|)b0>180: WDISP22 stop\+0xfffffe80184: 01 00 00 00 nop188: 11 c0 00 01 cba 18c <test_coprocessor\+(0x|)b8>188: WDISP22 stop\+0xfffffe7818c: 01 00 00 00 nop190: 31 c0 00 01 cba,a 194 <test_coprocessor\+(0x|)c0>190: WDISP22 stop\+0xfffffe70194: 01 00 00 00 nop198: 13 c0 00 01 cbne 19c <test_coprocessor\+(0x|)c8>198: WDISP22 stop\+0xfffffe6819c: 01 00 00 00 nop1a0: 33 c0 00 01 cbne,a 1a4 <test_coprocessor\+(0x|)d0>1a0: WDISP22 stop\+0xfffffe601a4: 01 00 00 00 nop1a8: 15 c0 00 01 cbnf 1ac <test_coprocessor\+(0x|)d8>1a8: WDISP22 stop\+0xfffffe581ac: 01 00 00 00 nop1b0: 35 c0 00 01 cbnf,a 1b4 <test_coprocessor\+(0x|)e0>1b0: WDISP22 stop\+0xfffffe501b4: 01 00 00 00 nop1b8: 17 c0 00 01 cbnef 1bc <test_coprocessor\+(0x|)e8>1b8: WDISP22 stop\+0xfffffe481bc: 01 00 00 00 nop1c0: 37 c0 00 01 cbnef,a 1c4 <test_coprocessor\+(0x|)f0>1c0: WDISP22 stop\+0xfffffe401c4: 01 00 00 00 nop1c8: 19 c0 00 01 cbnr 1cc <test_coprocessor\+(0x|)f8>1c8: WDISP22 stop\+0xfffffe381cc: 01 00 00 00 nop1d0: 39 c0 00 01 cbnr,a 1d4 <test_coprocessor\+(0x|)100>1d0: WDISP22 stop\+0xfffffe301d4: 01 00 00 00 nop1d8: 1b c0 00 01 cbner 1dc <test_coprocessor\+(0x|)108>1d8: WDISP22 stop\+0xfffffe281dc: 01 00 00 00 nop1e0: 3b c0 00 01 cbner,a 1e4 <test_coprocessor\+(0x|)110>1e0: WDISP22 stop\+0xfffffe201e4: 01 00 00 00 nop1e8: 1d c0 00 01 cbnfr 1ec <test_coprocessor\+(0x|)118>1e8: WDISP22 stop\+0xfffffe181ec: 01 00 00 00 nop1f0: 3d c0 00 01 cbnfr,a 1f4 <test_coprocessor\+(0x|)120>1f0: WDISP22 stop\+0xfffffe101f4: 01 00 00 00 nop1f8: 1f c0 00 01 cbnefr 1fc <test_coprocessor\+(0x|)128>1f8: WDISP22 stop\+0xfffffe081fc: 01 00 00 00 nop200: 3f c0 00 01 cbnefr,a 204 <test_coprocessor\+(0x|)130>200: WDISP22 stop\+0xfffffe00204: 01 00 00 00 nop