OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [ld/] [scripttempl/] [elf32xc16x.sc] - Rev 455

Go to most recent revision | Compare with Previous | Blame | View Log

cat <<EOF
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
ENTRY("_start")
MEMORY
{
        
        vectarea : o =0x00000, l = 0x0300 
        
        introm    : o = 0x00400, l = 0x16000
        /* The stack starts at the top of main ram.  */
        
        dram   : o = 0x8000 , l = 0xffff
        /* At the very top of the address space is the 8-bit area.  */
                
         ldata  : o =0x4000 ,l = 0x0200
}

SECTIONS
{
.init :
        {
          *(.init)
        } ${RELOCATING+ >introm}
 
.text :
        {
          *(.rodata) 
          *(.text.*)
          *(.text)
                  ${RELOCATING+ _etext = . ; }
        } ${RELOCATING+ > introm}
.data :
        {
          *(.data)
          *(.data.*)
          
          ${RELOCATING+ _edata = . ; }
        } ${RELOCATING+ > dram}

.bss :
        {
          ${RELOCATING+ _bss_start = . ;}
          *(.bss)
          *(COMMON)
          ${RELOCATING+ _end = . ;  }
        } ${RELOCATING+ > dram}

 .ldata :
         {
          *(.ldata)
         } ${RELOCATING+ > ldata}

  
  .vects :
          {
          *(.vects)
       } ${RELOCATING+ > vectarea}     

}
EOF

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.