URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [armv1-bad.l] - Rev 205
Compare with Previous | Blame | View Log
[^:]*: Assembler messages:[^:]*:4: Error: invalid pseudo operation -- `str r0,=0x00ff0000'[^:]*:5: Error: bad expression -- `ldr r0,{r1}'[^:]*:6: Error: bad instruction `cmpl r0,r0'[^:]*:7: Error: selected processor does not support `strh r0,\[r1\]'[^:]*:8: Warning: writeback of base register is UNPREDICTABLE[^:]*:9: Warning: writeback of base register when in register list is UNPREDICTABLE[^:]*:10: Warning: writeback of base register is UNPREDICTABLE[^:]*:12: Warning: if writeback register is in list, it must be the lowest reg in the list