OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [thumb2_pool.d] - Rev 301

Go to most recent revision | Compare with Previous | Blame | View Log

# as: -march=armv6t2
# objdump: -dr --prefix-addresses --show-raw-insn
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*

.*: +file format .*arm.*

Disassembly of section .text:
0+000 <[^>]+> 4e04              ldr     r6, \[pc, #16\] ; \(00+14 <[^>]+>\)
0+002 <[^>]+> 4904              ldr     r1, \[pc, #16\] ; \(00+14 <[^>]+>\)
0+004 <[^>]+> f8df 600c         ldr\.w  r6, \[pc, #12\] ; 00+14 <[^>]+>
0+008 <[^>]+> f8df 9008         ldr\.w  r9, \[pc, #8\]  ; 00+14 <[^>]+>
0+00c <[^>]+> bf00              nop
0+00e <[^>]+> f8df 5004         ldr\.w  r5, \[pc, #4\]  ; 00+14 <[^>]+>
0+012 <[^>]+> 4900              ldr     r1, \[pc, #0\]  ; \(00+14 <[^>]+>\)
0+014 <[^>]+> 12345678 ?        .word   0x12345678

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.