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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [ldstla-n64-sym32.d] - Rev 205

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#objdump: -dr
#as: -64 -msym32 -G8 -EB
#name: MIPS ld-st-la with sym32
#source: ldstla-sym32.s

.*file format .*

Disassembly .*:

0+00 <.*>:
#
# dla constants
#
.*      li      a0,0xa800
.*      dsll32  a0,a0,0x10
.*      li      a0,0xa800
.*      dsll32  a0,a0,0x10
.*      daddu   a0,a0,v1
.*      lui     a0,0x8000
.*      lui     a0,0x8000
.*      daddu   a0,a0,v1
.*      lui     a0,0x7fff
.*      ori     a0,a0,0x7ff8
.*      lui     a0,0x7fff
.*      ori     a0,a0,0x7ff8
.*      daddu   a0,a0,v1
.*      lui     a0,0x7fff
.*      ori     a0,a0,0xfff8
.*      lui     a0,0x7fff
.*      ori     a0,a0,0xfff8
.*      daddu   a0,a0,v1
.*      lui     a0,0x1234
.*      ori     a0,a0,0x5678
.*      dsll    a0,a0,0x10
.*      ori     a0,a0,0x9abc
.*      dsll    a0,a0,0x10
.*      ori     a0,a0,0xdef0
.*      lui     a0,0x1234
.*      ori     a0,a0,0x5678
.*      dsll    a0,a0,0x10
.*      ori     a0,a0,0x9abc
.*      dsll    a0,a0,0x10
.*      ori     a0,a0,0xdef0
.*      daddu   a0,a0,v1
#
# dla small_comm
#
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
#
# dla big_comm
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
#
# dla small_data
#
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,gp,0
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
#
# dla big_data
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
#
# dla extern
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu a0,a0,0
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
#
# lw constants
#
.*      li      a0,0xa800
.*      dsll32  a0,a0,0x10
.*      lw      a0,0\(a0\)
.*      li      a0,0xa800
.*      dsll32  a0,a0,0x10
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*      lui     a0,0x8000
.*      lw      a0,0\(a0\)
.*      lui     a0,0x8000
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*      lui     a0,0x7fff
.*      lw      a0,32760\(a0\)
.*      lui     a0,0x7fff
.*      daddu   a0,a0,v1
.*      lw      a0,32760\(a0\)
.*      li      a0,0x8000
.*      dsll    a0,a0,0x10
.*      lw      a0,-8\(a0\)
.*      li      a0,0x8000
.*      dsll    a0,a0,0x10
.*      daddu   a0,a0,v1
.*      lw      a0,-8\(a0\)
.*      lui     a0,0x1234
.*      ori     a0,a0,0x5678
.*      dsll    a0,a0,0x10
.*      ori     a0,a0,0x9abd
.*      dsll    a0,a0,0x10
.*      lw      a0,-8464\(a0\)
.*      lui     a0,0x1234
.*      ori     a0,a0,0x5678
.*      dsll    a0,a0,0x10
.*      ori     a0,a0,0x9abd
.*      dsll    a0,a0,0x10
.*      daddu   a0,a0,v1
.*      lw      a0,-8464\(a0\)
#
# lw small_comm
#
.*      lw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,v1,gp
.*      lw      a0,0\(a0\)
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,v1,gp
.*      lw      a0,0\(a0\)
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# lw big_comm
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# lw small_data
#
.*      lw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,v1,gp
.*      lw      a0,0\(a0\)
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,v1,gp
.*      lw      a0,0\(a0\)
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# lw big_data
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# lw extern
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   a0,a0,v1
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# sw constants
#
.*      li      at,0xa800
.*      dsll32  at,at,0x10
.*      sw      a0,0\(at\)
.*      li      at,0xa800
.*      dsll32  at,at,0x10
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*      lui     at,0x8000
.*      sw      a0,0\(at\)
.*      lui     at,0x8000
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*      lui     at,0x7fff
.*      sw      a0,32760\(at\)
.*      lui     at,0x7fff
.*      daddu   at,at,v1
.*      sw      a0,32760\(at\)
.*      li      at,0x8000
.*      dsll    at,at,0x10
.*      sw      a0,-8\(at\)
.*      li      at,0x8000
.*      dsll    at,at,0x10
.*      daddu   at,at,v1
.*      sw      a0,-8\(at\)
.*      lui     at,0x1234
.*      ori     at,at,0x5678
.*      dsll    at,at,0x10
.*      ori     at,at,0x9abd
.*      dsll    at,at,0x10
.*      sw      a0,-8464\(at\)
.*      lui     at,0x1234
.*      ori     at,at,0x5678
.*      dsll    at,at,0x10
.*      ori     at,at,0x9abd
.*      dsll    at,at,0x10
.*      daddu   at,at,v1
.*      sw      a0,-8464\(at\)
#
# sw small_comm
#
.*      sw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,v1,gp
.*      sw      a0,0\(at\)
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,v1,gp
.*      sw      a0,0\(at\)
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# sw big_comm
#
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# sw small_data
#
.*      sw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,v1,gp
.*      sw      a0,0\(at\)
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(gp\)
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,v1,gp
.*      sw      a0,0\(at\)
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# sw big_data
#
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# sw extern
#
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
#
# usw constants
#
.*      li      at,0xa800
.*      dsll32  at,at,0x10
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      li      at,0xa800
.*      dsll32  at,at,0x10
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x8000
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x8000
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x7fff
.*      ori     at,at,0x7ff8
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x7fff
.*      ori     at,at,0x7ff8
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x7fff
.*      ori     at,at,0xfff8
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x7fff
.*      ori     at,at,0xfff8
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x1234
.*      ori     at,at,0x5678
.*      dsll    at,at,0x10
.*      ori     at,at,0x9abc
.*      dsll    at,at,0x10
.*      ori     at,at,0xdef0
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x1234
.*      ori     at,at,0x5678
.*      dsll    at,at,0x10
.*      ori     at,at,0x9abc
.*      dsll    at,at,0x10
.*      ori     at,at,0xdef0
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# usw small_comm
#
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# usw big_comm
#
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_comm
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_comm\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# usw small_data
#
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      daddiu  at,gp,0
.*: R_MIPS_GPREL16      small_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# usw big_data
#
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_data
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 big_data\+0x3
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# usw extern
#
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 extern\+0x34000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
.*      lui     at,0x0
.*: R_MIPS_HI16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      d?addiu at,at,0
.*: R_MIPS_LO16 extern\+0xfffffffffffcc000
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddu   at,at,v1
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# with sym32 off
#
.*      lui     a0,0x0
.*: R_MIPS_HIGHEST      extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,a0,0
.*: R_MIPS_HIGHER       extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  at,at,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      dsll32  a0,a0,0x0
.*      daddu   a0,a0,at
.*      lui     a0,0x0
.*: R_MIPS_HIGHEST      extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,a0,0
.*: R_MIPS_HIGHER       extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      dsll32  a0,a0,0x0
.*      daddu   a0,a0,at
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HIGHEST      extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  at,at,0
.*: R_MIPS_HIGHER       extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      dsll    at,at,0x10
.*      daddiu  at,at,0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      dsll    at,at,0x10
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HIGHEST      extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  at,at,0
.*: R_MIPS_HIGHER       extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      dsll    at,at,0x10
.*      daddiu  at,at,0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      dsll    at,at,0x10
.*      daddiu  at,at,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#
# ...and back on again
#
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  a0,a0,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     a0,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lw      a0,0\(a0\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      sw      a0,0\(at\)
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      lui     at,0x0
.*: R_MIPS_HI16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      daddiu  at,at,0
.*: R_MIPS_LO16 extern
.*: R_MIPS_NONE .*
.*: R_MIPS_NONE .*
.*      swl     a0,0\(at\)
.*      swr     a0,3\(at\)
#pass

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