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#PROG: nm
#as: -mips32r2 -32
#name: MIPS16 intermix

0+[0-9a-f]+ t __call_stub_fp_m16_static16_d_d
0+[0-9a-f]+ t __call_stub_fp_m16_static16_d_l
0+[0-9a-f]+ t __call_stub_fp_m16_static1_d_d
0+[0-9a-f]+ t __call_stub_fp_m16_static1_d_l
0+[0-9a-f]+ t __call_stub_fp_m32_static16_d_d
0+[0-9a-f]+ t __call_stub_fp_m32_static16_d_l
0+[0-9a-f]+ t __call_stub_fp_m32_static1_d_d
0+[0-9a-f]+ t __call_stub_fp_m32_static1_d_l
0+[0-9a-f]+ t __call_stub_m16_static16_d
0+[0-9a-f]+ t __call_stub_m16_static16_dl
0+[0-9a-f]+ t __call_stub_m16_static16_dlld
0+[0-9a-f]+ t __call_stub_m16_static1_d
0+[0-9a-f]+ t __call_stub_m16_static1_dl
0+[0-9a-f]+ t __call_stub_m16_static1_dlld
0+[0-9a-f]+ t __call_stub_m32_static16_d
0+[0-9a-f]+ t __call_stub_m32_static16_dl
0+[0-9a-f]+ t __call_stub_m32_static16_dlld
0+[0-9a-f]+ t __call_stub_m32_static1_d
0+[0-9a-f]+ t __call_stub_m32_static1_dl
0+[0-9a-f]+ t __call_stub_m32_static1_dlld
0+[0-9a-f]+ t __fn_stub_m16_d
0+[0-9a-f]+ t __fn_stub_m16_d_d
0+[0-9a-f]+ t __fn_stub_m16_dl
0+[0-9a-f]+ t __fn_stub_m16_dlld
0+[0-9a-f]+ t __fn_stub_m16_static16_d
0+[0-9a-f]+ t __fn_stub_m16_static16_d_d
0+[0-9a-f]+ t __fn_stub_m16_static16_dl
0+[0-9a-f]+ t __fn_stub_m16_static16_dlld
0+[0-9a-f]+ t __fn_stub_m16_static1_d
0+[0-9a-f]+ t __fn_stub_m16_static1_d_d
0+[0-9a-f]+ t __fn_stub_m16_static1_dl
0+[0-9a-f]+ t __fn_stub_m16_static1_dlld
0+[0-9a-f]+ t __fn_stub_m16_static32_d
0+[0-9a-f]+ t __fn_stub_m16_static32_d_d
0+[0-9a-f]+ t __fn_stub_m16_static32_dl
0+[0-9a-f]+ t __fn_stub_m16_static32_dlld
0+[0-9a-f]+ t __fn_stub_m16_static_d
0+[0-9a-f]+ t __fn_stub_m16_static_d_d
0+[0-9a-f]+ t __fn_stub_m16_static_dl
0+[0-9a-f]+ t __fn_stub_m16_static_dlld
[       ]+ U __mips16_adddf3
[       ]+ U __mips16_fixdfsi
[       ]+ U __mips16_floatsidf
[       ]+ U __mips16_ret_df
0+[0-9a-f]+ T f16
0+[0-9a-f]+ T f32
0+[0-9a-f]+ T m16_d
0+[0-9a-f]+ T m16_d_d
0+[0-9a-f]+ T m16_d_l
0+[0-9a-f]+ T m16_dl
0+[0-9a-f]+ T m16_dlld
0+[0-9a-f]+ T m16_l
0+[0-9a-f]+ T m16_ld
0+[0-9a-f]+ t m16_static16_d
0+[0-9a-f]+ t m16_static16_d_d
0+[0-9a-f]+ t m16_static16_d_l
0+[0-9a-f]+ t m16_static16_dl
0+[0-9a-f]+ t m16_static16_dlld
0+[0-9a-f]+ t m16_static16_l
0+[0-9a-f]+ t m16_static16_ld
0+[0-9a-f]+ t m16_static1_d
0+[0-9a-f]+ t m16_static1_d_d
0+[0-9a-f]+ t m16_static1_d_l
0+[0-9a-f]+ t m16_static1_dl
0+[0-9a-f]+ t m16_static1_dlld
0+[0-9a-f]+ t m16_static1_l
0+[0-9a-f]+ t m16_static1_ld
0+[0-9a-f]+ t m16_static32_d
0+[0-9a-f]+ t m16_static32_d_d
0+[0-9a-f]+ t m16_static32_d_l
0+[0-9a-f]+ t m16_static32_dl
0+[0-9a-f]+ t m16_static32_dlld
0+[0-9a-f]+ t m16_static32_l
0+[0-9a-f]+ t m16_static32_ld
0+[0-9a-f]+ t m16_static_d
0+[0-9a-f]+ t m16_static_d_d
0+[0-9a-f]+ t m16_static_d_l
0+[0-9a-f]+ t m16_static_dl
0+[0-9a-f]+ t m16_static_dlld
0+[0-9a-f]+ t m16_static_l
0+[0-9a-f]+ t m16_static_ld
0+[0-9a-f]+ T m32_d
0+[0-9a-f]+ T m32_d_d
0+[0-9a-f]+ T m32_d_l
0+[0-9a-f]+ T m32_dl
0+[0-9a-f]+ T m32_dlld
0+[0-9a-f]+ T m32_l
0+[0-9a-f]+ T m32_ld
0+[0-9a-f]+ t m32_static16_d
0+[0-9a-f]+ t m32_static16_d_d
0+[0-9a-f]+ t m32_static16_d_l
0+[0-9a-f]+ t m32_static16_dl
0+[0-9a-f]+ t m32_static16_dlld
0+[0-9a-f]+ t m32_static16_l
0+[0-9a-f]+ t m32_static16_ld
0+[0-9a-f]+ t m32_static1_d
0+[0-9a-f]+ t m32_static1_d_d
0+[0-9a-f]+ t m32_static1_d_l
0+[0-9a-f]+ t m32_static1_dl
0+[0-9a-f]+ t m32_static1_dlld
0+[0-9a-f]+ t m32_static1_l
0+[0-9a-f]+ t m32_static1_ld
0+[0-9a-f]+ t m32_static32_d
0+[0-9a-f]+ t m32_static32_d_d
0+[0-9a-f]+ t m32_static32_d_l
0+[0-9a-f]+ t m32_static32_dl
0+[0-9a-f]+ t m32_static32_dlld
0+[0-9a-f]+ t m32_static32_l
0+[0-9a-f]+ t m32_static32_ld
0+[0-9a-f]+ t m32_static_d
0+[0-9a-f]+ t m32_static_d_d
0+[0-9a-f]+ t m32_static_d_l
0+[0-9a-f]+ t m32_static_dl
0+[0-9a-f]+ t m32_static_dlld
0+[0-9a-f]+ t m32_static_l
0+[0-9a-f]+ t m32_static_ld
#pass