URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [sparc/] [sparclet.md] - Rev 298
Go to most recent revision | Compare with Previous | Blame | View Log
;; Scheduling description for SPARClet.
;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; The SPARClet is a single-issue processor.
(define_automaton "sparclet")
(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet")
(define_cpu_unit "sl_store,sl_imul" "sparclet")
(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)")
(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)")
(define_insn_reservation "sl_ld" 3
(and (eq_attr "cpu" "tsc701")
(eq_attr "type" "load,sload"))
"sl_load_any, sl_load_any, sl_load_any")
(define_insn_reservation "sl_st" 3
(and (eq_attr "cpu" "tsc701")
(eq_attr "type" "store"))
"(sl_store+sl_load_all)*3")
(define_insn_reservation "sl_imul" 5
(and (eq_attr "cpu" "tsc701")
(eq_attr "type" "imul"))
"sl_imul*5")
Go to most recent revision | Compare with Previous | Blame | View Log