OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [config/] [xtensa/] [xtensa.opt] - Rev 310

Go to most recent revision | Compare with Previous | Blame | View Log

; Options for the Tensilica Xtensa port of the compiler.

; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

mconst16
Target Report Mask(CONST16)
Use CONST16 instruction to load constants

mfused-madd
Target Report Mask(FUSED_MADD)
Enable fused multiply/add and multiply/subtract FP instructions

mlongcalls
Target
Use indirect CALLXn instructions for large programs

mtarget-align
Target
Automatically align branch targets to reduce branch penalties

mtext-section-literals
Target
Intersperse literal pools with code in the text section

mserialize-volatile
Target Report Mask(SERIALIZE_VOLATILE)
-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.