OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20031220-1.c] - Rev 298

Go to most recent revision | Compare with Previous | Blame | View Log

/* PR optimization/13031  */
/* The following code used to ICE on alphaev67-*-* at -O2 with an
   unrecognizable instruction, caused by local register allocation
   substituting a register for a constant in a conditional branch.  */
 
void emit(int, int);
int f(void);
static int signals[5];
 
static inline void select(int sel, void *klass)
{
  emit(klass ? 0 : f(), signals[sel ? 0 : 1]);
}
 
void all(void *gil, void *l, void *icon)
{
  while (l)
    if (icon)
      select(0, gil);
}
 
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.