OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vreinterpretQs8_s64.c] - Rev 313

Compare with Previous | Blame | View Log

/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
/* This file was autogenerated by neon-testgen.  */
 
/* { dg-do assemble } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
 
#include "arm_neon.h"
 
void test_vreinterpretQs8_s64 (void)
{
  int8x16_t out_int8x16_t;
  int64x2_t arg0_int64x2_t;
 
  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
}
 
/* { dg-final { cleanup-saved-temps } } */
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.