OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse2-paddsw-1.c] - Rev 318

Compare with Previous | Blame | View Log

/* { dg-do run } */
/* { dg-options "-O2 -msse2" } */
/* { dg-require-effective-target sse2 } */
 
#ifndef CHECK_H
#define CHECK_H "sse2-check.h"
#endif
 
#ifndef TEST
#define TEST sse2_test
#endif
 
#include CHECK_H
 
#include <emmintrin.h>
 
static __m128i
__attribute__((noinline, unused))
test (__m128i s1, __m128i s2)
{
  return _mm_adds_epi16 (s1, s2); 
}
 
static void
TEST (void)
{
  union128i_w u, s1, s2;
  short e[8];
  int i, tmp;
 
  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
  u.x = test (s1.x, s2.x); 
 
  for (i = 0; i < 8; i++)
    {
      tmp = s1.a[i] + s2.a[i];
 
      if (tmp > 32767)
        tmp = 32767;
      if (tmp < -32768)
        tmp = -32768;
 
      e[i] = tmp;
    }
 
  if (check_union128i_w (u, e))
    abort ();
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.