OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse4_1-pmovzxwd.c] - Rev 318

Compare with Previous | Blame | View Log

/* { dg-do run } */
/* { dg-require-effective-target sse4 } */
/* { dg-options "-O2 -msse4.1" } */
 
#ifndef CHECK_H
#define CHECK_H "sse4_1-check.h"
#endif
 
#ifndef TEST
#define TEST sse4_1_test
#endif
 
#include CHECK_H
 
#include <smmintrin.h>
 
#define NUM 128
 
static void
TEST (void)
{
  union
    {
      __m128i x[NUM / 4];
      unsigned int i[NUM];
      unsigned short s[NUM * 2];
    } dst, src;
  int i;
 
  for (i = 0; i < NUM; i++)
    {
      src.s[(i % 4) + (i / 4) * 8] = i * i;
      if ((i % 4))
	src.s[(i % 4) + (i / 4) * 8] |= 0x8000;
    }
 
  for (i = 0; i < NUM; i += 4)
    dst.x [i / 4] = _mm_cvtepu16_epi32 (src.x [i / 4]);
 
  for (i = 0; i < NUM; i++)
    if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
      abort ();
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.