OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [fpr-moves-4.c] - Rev 321

Compare with Previous | Blame | View Log

/* { dg-options "-mabi=32 -mfp64 -O2 -EB" } */
 
NOMIPS16 double
foo (double d)
{
  register double l1 asm ("$8") = d;
  register double l2 asm ("$f20") = 0.0;
  asm ("#foo" : "=d" (l1) : "d" (l1));
  asm volatile ("#foo" :: "f" (l2));
  return l1;
}
 
/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */
/* { dg-final { scan-assembler "\tmfhc1\t\\\$8,\\\$f12\n" } } */
/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */
/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */
/* { dg-final { scan-assembler "\tmthc1\t\\\$8,\\\$f0\n" } } */
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.