OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-24.c] - Rev 322

Compare with Previous | Blame | View Log

/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-maltivec" } */
 
#include <altivec.h>
 
extern void abort (void);
 
typedef int v4si __attribute__ ((vector_size (16)));
 
#define MAGIC_NUMBER 12345
 
v4si my_vect;
int my_array[4] __attribute__ ((aligned (16)));
 
void initialize (int a)
{
  my_vect = (v4si) {0, a, 2, 3};
  vec_st (my_vect, 0, my_array);
}
 
int verify (void)
{
  if (my_array[1] != MAGIC_NUMBER)
    abort ();
}
 
int main (void)
{
  initialize (MAGIC_NUMBER);
  verify ();
  return 0;
}
 
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.