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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [ultrasp10.c] - Rev 326

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/* PR target/11965 */
/* Originator: <jk@tools.de> */
 
/* { dg-do run } */
/* { dg-require-effective-target ultrasparc_hw } */
/* { dg-options "-O -mcpu=ultrasparc" } */
 
/* This used to fail on 32-bit Ultrasparc because GCC emitted
   an invalid shift instruction.  */
 
 
static inline unsigned int shift(int n, unsigned int value)
{
  return value << n;
}
 
unsigned int val = 1;
 
int main(void)
{
  int i;
 
  for (i = 0; i < 4; i++)
    val = shift(32, val);
 
  return 0;
}
 

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