OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.5.1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [ultrasp10.c] - Rev 378

Go to most recent revision | Compare with Previous | Blame | View Log

/* PR target/11965 */
/* Originator: <jk@tools.de> */
 
/* { dg-do run } */
/* { dg-require-effective-target ultrasparc_hw } */
/* { dg-options "-O -mcpu=ultrasparc" } */
 
/* This used to fail on 32-bit Ultrasparc because GCC emitted
   an invalid shift instruction.  */
 
 
static inline unsigned int shift(int n, unsigned int value)
{
  return value << n;
}
 
unsigned int val = 1;
 
int main(void)
{
  int i;
 
  for (i = 0; i < 4; i++)
    val = shift(32, val);
 
  return 0;
}
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.