URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [m32r/] [arch.c] - Rev 297
Go to most recent revision | Compare with Previous | Blame | View Log
/* Simulator support for m32r. THIS FILE IS MACHINE GENERATED WITH CGEN. Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "sim-main.h" #include "bfd.h" const MACH *sim_machs[] = { #ifdef HAVE_CPU_M32RBF & m32r_mach, #endif #ifdef HAVE_CPU_M32RXF & m32rx_mach, #endif #ifdef HAVE_CPU_M32R2F & m32r2_mach, #endif 0 };
Go to most recent revision | Compare with Previous | Blame | View Log