OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [ChangeLog] - Rev 441

Go to most recent revision | Compare with Previous | Blame | View Log

2005-01-07  Andrew Cagney  <cagney@gnu.org>

        * configure.ac: Rename configure.in, require autoconf 2.59.
        * configure: Re-generate.

Tue Apr 18 16:32:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-rie-xx.s (test_rie_xx): New test.
        * Makefile.in (TESTS): Update.

Tue Feb 22 17:36:34 2000  Andrew Cagney  <cagney@b1.cygnus.com>

        * Makefile.in: Force d10v into operating mode.

Mon Jan  3 00:17:28 2000  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s ,
        t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s ,
        t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s ,
        t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s ,
        t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s ,
        t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests.  Check that an address
        exception occures when a word/two-word load/store is not word
        aligned.
        * Makefile.in (TESTS): Update.

Fri Oct 29 18:36:34 1999  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-mvtc.s: Check that the user can not modify the DM bit in the
        BPSW or DPSW.

Thu Oct 28 01:47:26 1999  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-mvtc.s: Update. Check that user can not modify DM bit.

Wed Sep  8 19:34:55 MDT 1999    Diego Novillo <dnovillo@cygnus.com>

        * t-ld-st.s: New file.
        * t-sac.s: New file.
        * t-sachi.s: New file.
        * t-slae.s: New file.

1999-01-13  Jason Molenda  (jsm@bugshack.cygnus.com)

        * t-sadd.s: New file.
        * Makefile.in (TESTS): Add t-sadd.

Mon Feb 16 09:20:57 1998  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-macros.i (VEC_*): Define.
        (DMAP_REG, DMAP_BASE, DMAP_MASK): Define.
        (IMAP[01]_REG): Define.

        * t-rdt.s (test_tdt): New file.

        * t-dbt.s (test_dbt): New file.

        * Makefile.in (TESTS): Add t-rdt and t-dbt.
        

Fri Feb 13 16:21:13 1998  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-sp.s: New test.
        * Makefile.in (TESTS): Update.

Wed Feb 11 17:58:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-macros.i: Update trap calls, func in r4, args in
        r0...
        (start): Force r0 to zero.

        * t-sub2w.s: Ditto.

Tue Dec  9 10:41:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-rte.s (success): New file.
        * Makefile.in: Update.

        * t-rep.s: Check rep repeats correct number of times.

Fri Dec  5 10:11:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S.

        * t-trap.s: New file.
        * Makefile.in (TESTS): Update.

Thu Dec  4 16:56:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-macros.i: Add definitions for PSW bits.

        * t-mvtc.s: New file.
        * Makefile.in (TESTS): Update.

Wed Dec  3 16:35:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-rac.s: New files.
        
        * t-macros.i: Add macros for checking psw and 2w quantities.

        * Makefile.in (TESTS): Update.

Tue Dec  2 11:01:36 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New
        files.
        
        * Makefile.in: Update.

Mon Nov 17 20:14:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-subi.s (test_subi): New file.
        * Makefile.in: Update.

Fri Nov 14 14:06:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-rep.s: New file. Test case of branch to RPT_E address.

Mon Nov 10 19:21:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>

        * t-macros.i (_start): New file.
        * t-rachi.s: New file.

        * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v
        directory.

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.