URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-sp.s] - Rev 437
Go to most recent revision | Compare with Previous | Blame | View Log
.include "t-macros.i" start ;;; Read/Write values to SPU/SPI loadpsw2 0 ldi sp, 0xdead loadpsw2 PSW_SM ldi sp, 0xbeef loadpsw2 0 check 1 sp 0xdead loadpsw2 PSW_SM check 2 sp 0xbeef exit0
Go to most recent revision | Compare with Previous | Blame | View Log