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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [cmmachs.cgs] - Rev 407
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# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond# mach: frv fr500 fr400.include "testutils.inc"start.global cmmachscmmachs:set_spr_immed 0x1b1b,cccr; Positive operandsset_spr_immed 0x0,msr0set_spr_immed 0x0,msr1set_accg_immed 0x0,accg0set_acc_immed 0x0,acc0set_accg_immed 0x0,accg1set_acc_immed 0x0,acc1set_fr_iimmed 2,3,fr7 ; multiply small numbersset_fr_iimmed 3,2,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1set_fr_iimmed 0,1,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1set_fr_iimmed 2,1,fr7 ; multiply by 1set_fr_iimmed 1,2,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0,0x8006,acc0test_accg_immed 0,accg1test_acc_limmed 0,0x8006,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0001,0x0006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0001,0x0006,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x4000,0x0007,acc0test_accg_immed 0,accg1test_acc_limmed 0x4000,0x0007,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x4000,0x0001,acc0test_accg_immed 0,accg1test_acc_limmed 0x4000,0x0001,acc1set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1set_fr_iimmed 1,0xfffe,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0xffff,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0xffff,acc1set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0set_fr_iimmed 0,0xfffe,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0xffff,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0xffff,acc1set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr8cmmachs fr7,fr8,acc0,cc0,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0xbffd,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0xbffd,acc1set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0x3ffd,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0x3ffd,acc1set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xbffd,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xbffd,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xc003,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xc003,acc1set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xc005,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xc005,acc1set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0x3ffec006,acc0test_accg_immed 0,accg1test_acc_immed 0x3ffec006,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0x7ffec006,acc0test_accg_immed 0,accg1test_acc_immed 0x7ffec006,acc1set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachs fr7,fr8,acc0,cc4,1;;;;;;;;;;;;test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xffff,0xffff,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xffff,0xffff,acc1set_accg_immed -128,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed -128,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr7set_fr_iimmed 1,0xffff,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x80,accg0test_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1set_fr_iimmed 0x0000,0x8000,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc4,1test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x80,accg0test_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1; Positive operandsset_spr_immed 0x0,msr0set_spr_immed 0x0,msr1set_accg_immed 0x0,accg0 ; saturationset_acc_immed 0x0,acc0set_accg_immed 0x0,accg1set_acc_immed 0x0,acc1set_fr_iimmed 2,3,fr7 ; multiply small numbersset_fr_iimmed 3,2,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1set_fr_iimmed 0,1,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1set_fr_iimmed 2,1,fr7 ; multiply by 1set_fr_iimmed 1,2,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0,0x8006,acc0test_accg_immed 0,accg1test_acc_limmed 0,0x8006,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0001,0x0006,acc0test_accg_immed 0,accg1test_acc_limmed 0x0001,0x0006,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x4000,0x0007,acc0test_accg_immed 0,accg1test_acc_limmed 0x4000,0x0007,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x4000,0x0001,acc0test_accg_immed 0,accg1test_acc_limmed 0x4000,0x0001,acc1set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1set_fr_iimmed 1,0xfffe,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0xffff,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0xffff,acc1set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0set_fr_iimmed 0,0xfffe,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0xffff,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0xffff,acc1set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr8cmmachs fr7,fr8,acc0,cc1,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0xbffd,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0xbffd,acc1set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x3fff,0x3ffd,acc0test_accg_immed 0,accg1test_acc_limmed 0x3fff,0x3ffd,acc1set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xbffd,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xbffd,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xc003,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xc003,acc1set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0xff,accg0test_acc_limmed 0xffff,0xc005,acc0test_accg_immed 0xff,accg1test_acc_limmed 0xffff,0xc005,acc1set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0x3ffec006,acc0test_accg_immed 0,accg1test_acc_immed 0x3ffec006,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0x7ffec006,acc0test_accg_immed 0,accg1test_acc_immed 0x7ffec006,acc1set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachs fr7,fr8,acc0,cc5,0test_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xffff,0xffff,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xffff,0xffff,acc1set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr7set_fr_iimmed 1,0xffff,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x80,accg0test_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1set_fr_iimmed 0x0000,0x8000,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc5,0test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x80,accg0test_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1; Positive operandsset_spr_immed 0x0,msr0set_spr_immed 0x0,msr1set_accg_immed 0x0,accg0set_acc_immed 0x0,acc0set_accg_immed 0x0,accg1set_acc_immed 0x0,acc1set_fr_iimmed 2,3,fr7 ; multiply small numbersset_fr_iimmed 3,2,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0,1,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 2,1,fr7 ; multiply by 1set_fr_iimmed 1,2,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1set_fr_iimmed 1,0xfffe,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0set_fr_iimmed 0,0xfffe,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr8cmmachs fr7,fr8,acc0,cc0,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr7set_fr_iimmed 1,0xffff,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1set_fr_iimmed 0x0000,0x8000,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc4,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1; Positive operandsset_spr_immed 0x0,msr0set_spr_immed 0x0,msr1set_accg_immed 0x0,accg0set_acc_immed 0x0,acc0set_accg_immed 0x0,accg1set_acc_immed 0x0,acc1set_fr_iimmed 2,3,fr7 ; multiply small numbersset_fr_iimmed 3,2,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0,1,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 2,1,fr7 ; multiply by 1set_fr_iimmed 1,2,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1set_fr_iimmed 1,0xfffe,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0set_fr_iimmed 0,0xfffe,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr8cmmachs fr7,fr8,acc0,cc1,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr7set_fr_iimmed 1,0xffff,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1set_fr_iimmed 0x0000,0x8000,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc5,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1; Positive operandsset_spr_immed 0x0,msr0set_spr_immed 0x0,msr1set_accg_immed 0x0,accg0set_acc_immed 0x0,acc0set_accg_immed 0x0,accg1set_acc_immed 0x0,acc1set_fr_iimmed 2,3,fr7 ; multiply small numbersset_fr_iimmed 3,2,fr8cmmachs fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0,1,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachs fr7,fr8,acc0,cc2,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 2,1,fr7 ; multiply by 1set_fr_iimmed 1,2,fr8cmmachs fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachs fr7,fr8,acc0,cc2,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachs fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc2,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr8cmmachs fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1set_fr_iimmed 1,0xfffe,fr8cmmachs fr7,fr8,acc0,cc2,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0set_fr_iimmed 0,0xfffe,fr8cmmachs fr7,fr8,acc0,cc2,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr8cmmachs fr7,fr8,acc0,cc2,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr8cmmachs fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr8cmmachs fr7,fr8,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr8cmmachs fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr8cmmachs fr7,fr8,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr8cmmachs fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachs fr7,fr8,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachs fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr7set_fr_iimmed 1,0xffff,fr8cmmachs fr7,fr8,acc0,cc6,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1set_fr_iimmed 0x0000,0x8000,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc6,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1;; Positive operandsset_spr_immed 0x0,msr0set_spr_immed 0x0,msr1set_accg_immed 0x0,accg0set_acc_immed 0x0,acc0set_accg_immed 0x0,accg1set_acc_immed 0x0,acc1set_fr_iimmed 2,3,fr7 ; multiply small numbersset_fr_iimmed 3,2,fr8cmmachs fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0,1,fr7 ; multiply by 0set_fr_iimmed 2,0,fr8cmmachs fr7,fr8,acc0,cc3,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 2,1,fr7 ; multiply by 1set_fr_iimmed 1,2,fr8cmmachs fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x3fff,2,fr7 ; 15 bit resultset_fr_iimmed 2,0x3fff,fr8cmmachs fr7,fr8,acc0,cc3,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,2,fr7 ; 16 bit resultset_fr_iimmed 2,0x4000,fr8cmmachs fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc3,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Mixed operandsset_fr_iimmed 2,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,2,fr8cmmachs fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1set_fr_iimmed 1,0xfffe,fr8cmmachs fr7,fr8,acc0,cc3,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0set_fr_iimmed 0,0xfffe,fr8cmmachs fr7,fr8,acc0,cc3,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit resultset_fr_iimmed 0xfffe,0x2001,fr8cmmachs fr7,fr8,acc0,cc3,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit resultset_fr_iimmed 0xfffe,0x4000,fr8cmmachs fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative resultset_fr_iimmed 0x8000,0x7fff,fr8cmmachs fr7,fr8,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbersset_fr_iimmed 0xfffd,0xfffe,fr8cmmachs fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1set_fr_iimmed 0xfffe,0xffff,fr8cmmachs fr7,fr8,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr8cmmachs fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_fr_iimmed 0x8000,0x8000,fr7 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr8cmmachs fr7,fr8,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0,acc0test_accg_immed 0,accg1test_acc_immed 0,acc1set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_fr_iimmed 1,1,fr7set_fr_iimmed 1,1,fr8cmmachs fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x7f,accg0 ; saturationtest_acc_immed 0xffffffff,acc0test_accg_immed 0x7f,accg1test_acc_immed 0xffffffff,acc1set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_fr_iimmed 0xffff,0,fr7set_fr_iimmed 1,0xffff,fr8cmmachs fr7,fr8,acc0,cc7,1test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1set_fr_iimmed 0x0000,0x8000,fr7 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr8cmmachs fr7,fr8,acc0,cc7,0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 2,1,0,msr1 ; msr1.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0x80,accg0 ; saturationtest_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1pass
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