URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [cxor.cgs] - Rev 450
Go to most recent revision | Compare with Previous | Blame | View Log
# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond# mach: all.include "testutils.inc"start.global cxorcxor:set_spr_immed 0x1b1b,cccrset_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0x5555,0x5555,gr8set_icc 0x07,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc0,1test_icc 0 1 1 1 icc0test_gr_limmed 0xffff,0xffff,gr8set_gr_immed 0x00000000,gr7set_gr_immed 0x00000000,gr8set_icc 0x08,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc0,1test_icc 1 0 0 0 icc0test_gr_immed 0x00000000,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0xaaaa,0xaaaa,gr8set_icc 0x0b,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc4,1test_icc 1 0 1 1 icc0test_gr_immed 0x00000000,gr8set_gr_limmed 0xdead,0x0000,gr7set_gr_limmed 0x0000,0xbeef,gr8set_icc 0x05,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc4,1test_icc 0 1 0 1 icc0test_gr_limmed 0xdead,0xbeef,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0x5555,0x5555,gr8set_icc 0x07,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc0,0test_icc 0 1 1 1 icc0test_gr_limmed 0x5555,0x5555,gr8set_gr_immed 0x00007fff,gr7set_gr_immed 0x00000000,gr8set_icc 0x08,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc0,0test_icc 1 0 0 0 icc0test_gr_immed 0x00000000,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0xaaaa,0xaaaa,gr8set_icc 0x0b,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc4,0test_icc 1 0 1 1 icc0test_gr_limmed 0xaaaa,0xaaaa,gr8set_gr_limmed 0xdead,0x0000,gr7set_gr_limmed 0x0000,0xbeef,gr8set_icc 0x05,0 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc4,0test_icc 0 1 0 1 icc0test_gr_limmed 0x0000,0xbeef,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0x5555,0x5555,gr8set_icc 0x07,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc1,0test_icc 0 1 1 1 icc1test_gr_limmed 0xffff,0xffff,gr8set_gr_immed 0x00000000,gr7set_gr_immed 0x00000000,gr8set_icc 0x08,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc1,0test_icc 1 0 0 0 icc1test_gr_immed 0x00000000,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0xaaaa,0xaaaa,gr8set_icc 0x0b,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc5,0test_icc 1 0 1 1 icc1test_gr_immed 0x00000000,gr8set_gr_limmed 0xdead,0x0000,gr7set_gr_limmed 0x0000,0xbeef,gr8set_icc 0x05,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc5,0test_icc 0 1 0 1 icc1test_gr_limmed 0xdead,0xbeef,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0x5555,0x5555,gr8set_icc 0x07,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc1,1test_icc 0 1 1 1 icc1test_gr_limmed 0x5555,0x5555,gr8set_gr_immed 0x00007fff,gr7set_gr_immed 0x00000000,gr8set_icc 0x08,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc1,1test_icc 1 0 0 0 icc1test_gr_immed 0x00000000,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0xaaaa,0xaaaa,gr8set_icc 0x0b,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc5,1test_icc 1 0 1 1 icc1test_gr_limmed 0xaaaa,0xaaaa,gr8set_gr_limmed 0xdead,0x0000,gr7set_gr_limmed 0x0000,0xbeef,gr8set_icc 0x05,1 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc5,1test_icc 0 1 0 1 icc1test_gr_limmed 0x0000,0xbeef,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0x5555,0x5555,gr8set_icc 0x07,2 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc2,0test_icc 0 1 1 1 icc2test_gr_limmed 0x5555,0x5555,gr8set_gr_immed 0x00007fff,gr7set_gr_immed 0x00000000,gr8set_icc 0x08,2 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc2,0test_icc 1 0 0 0 icc2test_gr_immed 0x00000000,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0xaaaa,0xaaaa,gr8set_icc 0x0b,2 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc6,1test_icc 1 0 1 1 icc2test_gr_limmed 0xaaaa,0xaaaa,gr8set_gr_limmed 0xdead,0x0000,gr7set_gr_limmed 0x0000,0xbeef,gr8set_icc 0x05,2 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc6,1test_icc 0 1 0 1 icc2test_gr_limmed 0x0000,0xbeef,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0x5555,0x5555,gr8set_icc 0x07,3 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc3,0test_icc 0 1 1 1 icc3test_gr_limmed 0x5555,0x5555,gr8set_gr_immed 0x00007fff,gr7set_gr_immed 0x00000000,gr8set_icc 0x08,3 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc3,0test_icc 1 0 0 0 icc3test_gr_immed 0x00000000,gr8set_gr_limmed 0xaaaa,0xaaaa,gr7set_gr_limmed 0xaaaa,0xaaaa,gr8set_icc 0x0b,3 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc7,1test_icc 1 0 1 1 icc3test_gr_limmed 0xaaaa,0xaaaa,gr8set_gr_limmed 0xdead,0x0000,gr7set_gr_limmed 0x0000,0xbeef,gr8set_icc 0x05,3 ; Set mask opposite of expectedcxor gr7,gr8,gr8,cc7,1test_icc 0 1 0 1 icc3test_gr_limmed 0x0000,0xbeef,gr8pass
Go to most recent revision | Compare with Previous | Blame | View Log