URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbgelr.cgs] - Rev 450
Go to most recent revision | Compare with Previous | Blame | View Log
# frv testcase for fcbgelr $FCCi,$ccond,$hint# mach: all.include "testutils.inc"start.global fcbgelrfcbgelr:; ccond is trueset_spr_immed 128,lcrset_spr_addr bad,lrset_fcc 0x0 0fcbgelr fcc0,0,0set_spr_addr bad,lrset_fcc 0x1 1fcbgelr fcc1,0,1set_spr_addr ok3,lrset_fcc 0x2 2fcbgelr fcc2,0,2failok3:set_spr_addr ok4,lrset_fcc 0x3 3fcbgelr fcc3,0,3failok4:set_spr_addr bad,lrset_fcc 0x4 0fcbgelr fcc0,0,0set_spr_addr bad,lrset_fcc 0x5 1fcbgelr fcc1,0,1set_spr_addr ok7,lrset_fcc 0x6 2fcbgelr fcc2,0,2failok7:set_spr_addr ok8,lrset_fcc 0x7 3fcbgelr fcc3,0,3failok8:set_spr_addr ok9,lrset_fcc 0x8 0fcbgelr fcc0,0,0failok9:set_spr_addr oka,lrset_fcc 0x9 1fcbgelr fcc1,0,1failoka:set_spr_addr okb,lrset_fcc 0xa 2fcbgelr fcc2,0,2failokb:set_spr_addr okc,lrset_fcc 0xb 3fcbgelr fcc3,0,3failokc:set_spr_addr okd,lrset_fcc 0xc 0fcbgelr fcc0,0,0failokd:set_spr_addr oke,lrset_fcc 0xd 1fcbgelr fcc1,0,1failoke:set_spr_addr okf,lrset_fcc 0xe 2fcbgelr fcc2,0,2failokf:set_spr_addr okg,lrset_fcc 0xf 3fcbgelr fcc3,0,3failokg:; ccond is trueset_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x0 0fcbgelr fcc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x1 1fcbgelr fcc1,1,1set_spr_immed 1,lcrset_spr_addr okj,lrset_fcc 0x2 2fcbgelr fcc2,1,2failokj:set_spr_immed 1,lcrset_spr_addr okk,lrset_fcc 0x3 3fcbgelr fcc3,1,3failokk:set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x4 0fcbgelr fcc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x5 1fcbgelr fcc1,1,1set_spr_immed 1,lcrset_spr_addr okn,lrset_fcc 0x6 2fcbgelr fcc2,1,2failokn:set_spr_immed 1,lcrset_spr_addr oko,lrset_fcc 0x7 3fcbgelr fcc3,1,3failoko:set_spr_immed 1,lcrset_spr_addr okp,lrset_fcc 0x8 0fcbgelr fcc0,1,0failokp:set_spr_immed 1,lcrset_spr_addr okq,lrset_fcc 0x9 1fcbgelr fcc1,1,1failokq:set_spr_immed 1,lcrset_spr_addr okr,lrset_fcc 0xa 2fcbgelr fcc2,1,2failokr:set_spr_immed 1,lcrset_spr_addr oks,lrset_fcc 0xb 3fcbgelr fcc3,1,3failoks:set_spr_immed 1,lcrset_spr_addr okt,lrset_fcc 0xc 0fcbgelr fcc0,1,0failokt:set_spr_immed 1,lcrset_spr_addr oku,lrset_fcc 0xd 1fcbgelr fcc1,1,1failoku:set_spr_immed 1,lcrset_spr_addr okv,lrset_fcc 0xe 2fcbgelr fcc2,1,2failokv:set_spr_immed 1,lcrset_spr_addr okw,lrset_fcc 0xf 3fcbgelr fcc3,1,3failokw:; ccond is falseset_spr_immed 128,lcrset_fcc 0x0 0fcbgelr fcc0,1,0set_fcc 0x1 1fcbgelr fcc1,1,1set_fcc 0x2 2fcbgelr fcc2,1,2set_fcc 0x3 3fcbgelr fcc3,1,3set_fcc 0x4 0fcbgelr fcc0,1,0set_fcc 0x5 1fcbgelr fcc1,1,1set_fcc 0x6 2fcbgelr fcc2,1,2set_fcc 0x7 3fcbgelr fcc3,1,3set_fcc 0x8 0fcbgelr fcc0,1,0set_fcc 0x9 1fcbgelr fcc1,1,1set_fcc 0xa 2fcbgelr fcc2,1,2set_fcc 0xb 3fcbgelr fcc3,1,3set_fcc 0xc 0fcbgelr fcc0,1,0set_fcc 0xd 1fcbgelr fcc1,1,1set_fcc 0xe 2fcbgelr fcc2,1,2set_fcc 0xf 3fcbgelr fcc3,1,3; ccond is falseset_spr_immed 1,lcrset_fcc 0x0 0fcbgelr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x1 1fcbgelr fcc1,0,1set_spr_immed 1,lcrset_fcc 0x2 2fcbgelr fcc2,0,2set_spr_immed 1,lcrset_fcc 0x3 3fcbgelr fcc3,0,3set_spr_immed 1,lcrset_fcc 0x4 0fcbgelr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x5 1fcbgelr fcc1,0,1set_spr_immed 1,lcrset_fcc 0x6 2fcbgelr fcc2,0,2set_spr_immed 1,lcrset_fcc 0x7 3fcbgelr fcc3,0,3set_spr_immed 1,lcrset_fcc 0x8 0fcbgelr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x9 1fcbgelr fcc1,0,1set_spr_immed 1,lcrset_fcc 0xa 2fcbgelr fcc2,0,2set_spr_immed 1,lcrset_fcc 0xb 3fcbgelr fcc3,0,3set_spr_immed 1,lcrset_fcc 0xc 0fcbgelr fcc0,0,0set_spr_immed 1,lcrset_fcc 0xd 1fcbgelr fcc1,0,1set_spr_immed 1,lcrset_fcc 0xe 2fcbgelr fcc2,0,2set_spr_immed 1,lcrset_fcc 0xf 3fcbgelr fcc3,0,3passbad:fail
Go to most recent revision | Compare with Previous | Blame | View Log