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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbltlr.cgs] - Rev 272
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# frv testcase for fcbltlr $FCCi,$ccond,$hint# mach: all.include "testutils.inc"start.global fcbltlrfcbltlr:; ccond is trueset_spr_immed 128,lcrset_spr_addr bad,lrset_fcc 0x0 0fcbltlr fcc0,0,0set_spr_addr bad,lrset_fcc 0x1 1fcbltlr fcc1,0,1set_spr_addr bad,lrset_fcc 0x2 2fcbltlr fcc2,0,2set_spr_addr bad,lrset_fcc 0x3 3fcbltlr fcc3,0,3set_spr_addr ok5,lrset_fcc 0x4 0fcbltlr fcc0,0,0failok5:set_spr_addr ok6,lrset_fcc 0x5 1fcbltlr fcc1,0,1failok6:set_spr_addr ok7,lrset_fcc 0x6 2fcbltlr fcc2,0,2failok7:set_spr_addr ok8,lrset_fcc 0x7 3fcbltlr fcc3,0,3failok8:set_spr_addr bad,lrset_fcc 0x8 0fcbltlr fcc0,0,0set_spr_addr bad,lrset_fcc 0x9 1fcbltlr fcc1,0,1set_spr_addr bad,lrset_fcc 0xa 2fcbltlr fcc2,0,2set_spr_addr bad,lrset_fcc 0xb 3fcbltlr fcc3,0,3set_spr_addr okd,lrset_fcc 0xc 0fcbltlr fcc0,0,0failokd:set_spr_addr oke,lrset_fcc 0xd 1fcbltlr fcc1,0,1failoke:set_spr_addr okf,lrset_fcc 0xe 2fcbltlr fcc2,0,2failokf:set_spr_addr okg,lrset_fcc 0xf 3fcbltlr fcc3,0,3failokg:; ccond is trueset_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x0 0fcbltlr fcc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x1 1fcbltlr fcc1,1,1set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x2 2fcbltlr fcc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x3 3fcbltlr fcc3,1,3set_spr_immed 1,lcrset_spr_addr okl,lrset_fcc 0x4 0fcbltlr fcc0,1,0failokl:set_spr_immed 1,lcrset_spr_addr okm,lrset_fcc 0x5 1fcbltlr fcc1,1,1failokm:set_spr_immed 1,lcrset_spr_addr okn,lrset_fcc 0x6 2fcbltlr fcc2,1,2failokn:set_spr_immed 1,lcrset_spr_addr oko,lrset_fcc 0x7 3fcbltlr fcc3,1,3failoko:set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x8 0fcbltlr fcc0,1,0set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0x9 1fcbltlr fcc1,1,1set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0xa 2fcbltlr fcc2,1,2set_spr_immed 1,lcrset_spr_addr bad,lrset_fcc 0xb 3fcbltlr fcc3,1,3set_spr_immed 1,lcrset_spr_addr okt,lrset_fcc 0xc 0fcbltlr fcc0,1,0failokt:set_spr_immed 1,lcrset_spr_addr oku,lrset_fcc 0xd 1fcbltlr fcc1,1,1failoku:set_spr_immed 1,lcrset_spr_addr okv,lrset_fcc 0xe 2fcbltlr fcc2,1,2failokv:set_spr_immed 1,lcrset_spr_addr okw,lrset_fcc 0xf 3fcbltlr fcc3,1,3failokw:; ccond is falseset_spr_immed 128,lcrset_fcc 0x0 0fcbltlr fcc0,1,0set_fcc 0x1 1fcbltlr fcc1,1,1set_fcc 0x2 2fcbltlr fcc2,1,2set_fcc 0x3 3fcbltlr fcc3,1,3set_fcc 0x4 0fcbltlr fcc0,1,0set_fcc 0x5 1fcbltlr fcc1,1,1set_fcc 0x6 2fcbltlr fcc2,1,2set_fcc 0x7 3fcbltlr fcc3,1,3set_fcc 0x8 0fcbltlr fcc0,1,0set_fcc 0x9 1fcbltlr fcc1,1,1set_fcc 0xa 2fcbltlr fcc2,1,2set_fcc 0xb 3fcbltlr fcc3,1,3set_fcc 0xc 0fcbltlr fcc0,1,0set_fcc 0xd 1fcbltlr fcc1,1,1set_fcc 0xe 2fcbltlr fcc2,1,2set_fcc 0xf 3fcbltlr fcc3,1,3; ccond is falseset_spr_immed 1,lcrset_fcc 0x0 0fcbltlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x1 1fcbltlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0x2 2fcbltlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0x3 3fcbltlr fcc3,0,3set_spr_immed 1,lcrset_fcc 0x4 0fcbltlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x5 1fcbltlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0x6 2fcbltlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0x7 3fcbltlr fcc3,0,3set_spr_immed 1,lcrset_fcc 0x8 0fcbltlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0x9 1fcbltlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0xa 2fcbltlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0xb 3fcbltlr fcc3,0,3set_spr_immed 1,lcrset_fcc 0xc 0fcbltlr fcc0,0,0set_spr_immed 1,lcrset_fcc 0xd 1fcbltlr fcc1,0,1set_spr_immed 1,lcrset_fcc 0xe 2fcbltlr fcc2,0,2set_spr_immed 1,lcrset_fcc 0xf 3fcbltlr fcc3,0,3passbad:fail
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