URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbralr.cgs] - Rev 272
Go to most recent revision | Compare with Previous | Blame | View Log
# frv testcase for fcbralr $ccond# mach: all.include "testutils.inc"start.global fcbralrfcbralr:; ccond is trueset_spr_immed 128,lcrset_spr_addr ok1,lrset_fcc 0x0 0fcbralr 0failok1:set_spr_addr ok2,lrset_fcc 0x1 1fcbralr 0failok2:set_spr_addr ok3,lrset_fcc 0x2 2fcbralr 0failok3:set_spr_addr ok4,lrset_fcc 0x3 3fcbralr 0failok4:set_spr_addr ok5,lrset_fcc 0x4 0fcbralr 0failok5:set_spr_addr ok6,lrset_fcc 0x5 1fcbralr 0failok6:set_spr_addr ok7,lrset_fcc 0x6 2fcbralr 0failok7:set_spr_addr ok8,lrset_fcc 0x7 3fcbralr 0failok8:set_spr_addr ok9,lrset_fcc 0x8 0fcbralr 0failok9:set_spr_addr oka,lrset_fcc 0x9 1fcbralr 0failoka:set_spr_addr okb,lrset_fcc 0xa 2fcbralr 0failokb:set_spr_addr okc,lrset_fcc 0xb 3fcbralr 0failokc:set_spr_addr okd,lrset_fcc 0xc 0fcbralr 0failokd:set_spr_addr oke,lrset_fcc 0xd 1fcbralr 0failoke:set_spr_addr okf,lrset_fcc 0xe 2fcbralr 0failokf:set_spr_addr okg,lrset_fcc 0xf 3fcbralr 0failokg:; ccond is trueset_spr_immed 1,lcrset_spr_addr okh,lrset_fcc 0x0 0fcbralr 1failokh:set_spr_immed 1,lcrset_spr_addr oki,lrset_fcc 0x1 1fcbralr 1failoki:set_spr_immed 1,lcrset_spr_addr okj,lrset_fcc 0x2 2fcbralr 1failokj:set_spr_immed 1,lcrset_spr_addr okk,lrset_fcc 0x3 3fcbralr 1failokk:set_spr_immed 1,lcrset_spr_addr okl,lrset_fcc 0x4 0fcbralr 1failokl:set_spr_immed 1,lcrset_spr_addr okm,lrset_fcc 0x5 1fcbralr 1failokm:set_spr_immed 1,lcrset_spr_addr okn,lrset_fcc 0x6 2fcbralr 1failokn:set_spr_immed 1,lcrset_spr_addr oko,lrset_fcc 0x7 3fcbralr 1failoko:set_spr_immed 1,lcrset_spr_addr okp,lrset_fcc 0x8 0fcbralr 1failokp:set_spr_immed 1,lcrset_spr_addr okq,lrset_fcc 0x9 1fcbralr 1failokq:set_spr_immed 1,lcrset_spr_addr okr,lrset_fcc 0xa 2fcbralr 1failokr:set_spr_immed 1,lcrset_spr_addr oks,lrset_fcc 0xb 3fcbralr 1failoks:set_spr_immed 1,lcrset_spr_addr okt,lrset_fcc 0xc 0fcbralr 1failokt:set_spr_immed 1,lcrset_spr_addr oku,lrset_fcc 0xd 1fcbralr 1failoku:set_spr_immed 1,lcrset_spr_addr okv,lrset_fcc 0xe 2fcbralr 1failokv:set_spr_immed 1,lcrset_spr_addr okw,lrset_fcc 0xf 3fcbralr 1failokw:; ccond is falseset_spr_immed 128,lcrset_fcc 0x0 0fcbralr 1set_fcc 0x1 1fcbralr 1set_fcc 0x2 2fcbralr 1set_fcc 0x3 3fcbralr 1set_fcc 0x4 0fcbralr 1set_fcc 0x5 1fcbralr 1set_fcc 0x6 2fcbralr 1set_fcc 0x7 3fcbralr 1set_fcc 0x8 0fcbralr 1set_fcc 0x9 1fcbralr 1set_fcc 0xa 2fcbralr 1set_fcc 0xb 3fcbralr 1set_fcc 0xc 0fcbralr 1set_fcc 0xd 1fcbralr 1set_fcc 0xe 2fcbralr 1set_fcc 0xf 3fcbralr 1; ccond is falseset_spr_immed 1,lcrset_fcc 0x0 0fcbralr 0set_spr_immed 1,lcrset_fcc 0x1 1fcbralr 0set_spr_immed 1,lcrset_fcc 0x2 2fcbralr 0set_spr_immed 1,lcrset_fcc 0x3 3fcbralr 0set_spr_immed 1,lcrset_fcc 0x4 0fcbralr 0set_spr_immed 1,lcrset_fcc 0x5 1fcbralr 0set_spr_immed 1,lcrset_fcc 0x6 2fcbralr 0set_spr_immed 1,lcrset_fcc 0x7 3fcbralr 0set_spr_immed 1,lcrset_fcc 0x8 0fcbralr 0set_spr_immed 1,lcrset_fcc 0x9 1fcbralr 0set_spr_immed 1,lcrset_fcc 0xa 2fcbralr 0set_spr_immed 1,lcrset_fcc 0xb 3fcbralr 0set_spr_immed 1,lcrset_fcc 0xc 0fcbralr 0set_spr_immed 1,lcrset_fcc 0xd 1fcbralr 0set_spr_immed 1,lcrset_fcc 0xe 2fcbralr 0set_spr_immed 1,lcrset_fcc 0xf 3fcbralr 0pass
Go to most recent revision | Compare with Previous | Blame | View Log