OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcklg.cgs] - Rev 272

Go to most recent revision | Compare with Previous | Blame | View Log

# frv testcase for fcklg $FCCi,$CCj_float
# mach: all

        .include "testutils.inc"

        start

        .global fcklg
fcklg:
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x0 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1b9b,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x1 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1b9b,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x2 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x3 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x4 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x5 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x6 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x7 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x8 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1b9b,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0x9 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1b9b,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0xa 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0xb 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0xc 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0xd 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0xe 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        set_spr_immed   0x1b1b,cccr
        set_fcc         0xf 0
        fcklg           fcc0,cc3
        test_spr_immed  0x1bdb,cccr

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.