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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [mcmpuh.cgs] - Rev 272
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# frv testcase for mcmpuh $FRi,$FRj,$FCCk# mach: all.include "testutils.inc"start.global mcmpuhmcmpuh:set_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x7fff,0x7fff,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x8,1set_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x7fff,0x8000,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0xb,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x4,1set_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x7fff,fr11set_fcc 0xb,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x4,0test_fcc 0x8,1set_fr_iimmed 0x7fff,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr11set_fcc 0xb,0 ; Set mask opposite of expectedset_fcc 0xb,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x4,0test_fcc 0x4,1set_fr_iimmed 0x7fff,0x8000,fr10set_fr_iimmed 0x7fff,0x7fff,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0xd,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x2,1set_fr_iimmed 0x7fff,0x8000,fr10set_fr_iimmed 0x7fff,0x8000,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x8,1set_fr_iimmed 0x7fff,0x8000,fr10set_fr_iimmed 0x8000,0x7fff,fr11set_fcc 0xb,0 ; Set mask opposite of expectedset_fcc 0xd,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x4,0test_fcc 0x2,1set_fr_iimmed 0x7fff,0x8000,fr10set_fr_iimmed 0x8000,0x8000,fr11set_fcc 0xb,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x4,0test_fcc 0x8,1set_fr_iimmed 0x8000,0x7fff,fr10set_fr_iimmed 0x7fff,0x7fff,fr11set_fcc 0xd,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x2,0test_fcc 0x8,1set_fr_iimmed 0x8000,0x7fff,fr10set_fr_iimmed 0x7fff,0x8000,fr11set_fcc 0xd,0 ; Set mask opposite of expectedset_fcc 0xb,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x2,0test_fcc 0x4,1set_fr_iimmed 0x8000,0x7fff,fr10set_fr_iimmed 0x8000,0x7fff,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x8,1set_fr_iimmed 0x8000,0x7fff,fr10set_fr_iimmed 0x8000,0x8000,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0xb,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x4,1set_fr_iimmed 0x8000,0x8000,fr10set_fr_iimmed 0x7fff,0x7fff,fr11set_fcc 0xd,0 ; Set mask opposite of expectedset_fcc 0xd,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x2,0test_fcc 0x2,1set_fr_iimmed 0x8000,0x8000,fr10set_fr_iimmed 0x7fff,0x8000,fr11set_fcc 0xd,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x2,0test_fcc 0x8,1set_fr_iimmed 0x8000,0x8000,fr10set_fr_iimmed 0x8000,0x7fff,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0xd,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x2,1set_fr_iimmed 0x8000,0x8000,fr10set_fr_iimmed 0x8000,0x8000,fr11set_fcc 0x7,0 ; Set mask opposite of expectedset_fcc 0x7,1 ; Set mask opposite of expectedmcmpuh fr10,fr11,fcc0test_fcc 0x8,0test_fcc 0x8,1pass
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