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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [mqmacxhs.cgs] - Rev 272
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# frv testcase for mqmacxhs $GRi,$GRj,$ACCk# mach: fr400.include "testutils.inc"start.global mqmacxhsmqmacxhs:; Positive operandsset_fr_iimmed 2,3,fr8 ; multiply small numbersset_fr_iimmed 2,3,fr10set_fr_iimmed 0,1,fr9 ; multiply by 0set_fr_iimmed 0,2,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 6,acc0test_accg_immed 0,accg1test_acc_immed 6,acc1test_accg_immed 0,accg2test_acc_immed 0,acc2test_accg_immed 0,accg3test_acc_immed 0,acc3set_fr_iimmed 2,1,fr8 ; multiply by 1set_fr_iimmed 2,1,fr10set_fr_iimmed 0x3fff,2,fr9 ; 15 bit resultset_fr_iimmed 0x3fff,2,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 8,acc0test_accg_immed 0,accg1test_acc_immed 8,acc1test_accg_immed 0,accg2test_acc_limmed 0,0x7ffe,acc2test_accg_immed 0,accg3test_acc_limmed 0,0x7ffe,acc3set_fr_iimmed 0x4000,2,fr8 ; 16 bit resultset_fr_iimmed 0x4000,2,fr10set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive resultset_fr_iimmed 0x7fff,0x7fff,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8008,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8008,acc1test_accg_immed 0,accg2test_acc_limmed 0x3fff,0x7fff,acc2test_accg_immed 0,accg3test_acc_limmed 0x3fff,0x7fff,acc3; Mixed operandsset_fr_iimmed 2,0xfffd,fr8 ; multiply small numbersset_fr_iimmed 2,0xfffd,fr10set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1set_fr_iimmed 0xfffe,1,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8002,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8002,acc1test_accg_immed 0,accg2test_acc_limmed 0x3fff,0x7ffd,acc2test_accg_immed 0,accg3test_acc_limmed 0x3fff,0x7ffd,acc3set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0set_fr_iimmed 0xfffe,0,fr10set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit resultset_fr_iimmed 0x2001,0xfffe,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x8002,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x8002,acc1test_accg_immed 0,accg2test_acc_limmed 0x3fff,0x3ffb,acc2test_accg_immed 0,accg3test_acc_limmed 0x3fff,0x3ffb,acc3set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit resultset_fr_iimmed 0x4000,0xfffe,fr10set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative resultset_fr_iimmed 0x7fff,0x8000,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x0002,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x0002,acc1test_accg_immed 0xff,accg2test_acc_limmed 0xffff,0xbffb,acc2test_accg_immed 0xff,accg3test_acc_limmed 0xffff,0xbffb,acc3; Negative operandsset_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbersset_fr_iimmed 0xfffe,0xfffd,fr10set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1set_fr_iimmed 0xffff,0xfffe,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_limmed 0x0000,0x0008,acc0test_accg_immed 0,accg1test_acc_limmed 0x0000,0x0008,acc1test_accg_immed 0xff,accg2test_acc_limmed 0xffff,0xbffd,acc2test_accg_immed 0xff,accg3test_acc_limmed 0xffff,0xbffd,acc3set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive resultset_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x8000,0x8000,fr9 ; max positive resultset_fr_iimmed 0x8000,0x8000,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not settest_accg_immed 0,accg0test_acc_immed 0x3fff0009,acc0test_accg_immed 0,accg1test_acc_immed 0x3fff0009,acc1test_accg_immed 0,accg2test_acc_immed 0x3fffbffd,acc2test_accg_immed 0,accg3test_acc_immed 0x3fffbffd,acc3set_accg_immed 0x7f,accg0 ; saturationset_acc_immed 0xffffffff,acc0set_accg_immed 0x7f,accg1set_acc_immed 0xffffffff,acc1set_accg_immed 0x7f,accg2 ; saturationset_acc_immed 0xffffffff,acc2set_accg_immed 0x7f,accg3set_acc_immed 0xffffffff,acc3set_fr_iimmed 1,1,fr8set_fr_iimmed 1,1,fr10set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x7f,accg0test_acc_limmed 0xffff,0xffff,acc0test_accg_immed 0x7f,accg1test_acc_limmed 0xffff,0xffff,acc1test_accg_immed 0x7f,accg2test_acc_limmed 0xffff,0xffff,acc2test_accg_immed 0x7f,accg3test_acc_limmed 0xffff,0xffff,acc3set_accg_immed 0x80,accg0 ; saturationset_acc_immed 0,acc0set_accg_immed 0x80,accg1set_acc_immed 0,acc1set_accg_immed 0x80,accg2 ; saturationset_acc_immed 0,acc2set_accg_immed 0x80,accg3set_acc_immed 0,acc3set_fr_iimmed 0xffff,0,fr8set_fr_iimmed 0xffff,1,fr10set_fr_iimmed 0x0000,0x8000,fr9 ; saturationset_fr_iimmed 0x7fff,0x7fff,fr11mqmacxhs fr8,fr10,acc0test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf is settest_spr_bits 1,0,1,msr0 ; msr0.aovf is settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is settest_accg_immed 0x80,accg0test_acc_immed 0,acc0test_accg_immed 0x80,accg1test_acc_immed 0,acc1test_accg_immed 0x80,accg2test_acc_immed 0,acc2test_accg_immed 0x80,accg3test_acc_immed 0,acc3pass
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