Subversion Repositories openrisc_2011-10-31

# frv testcase for mp_exception
# mach: frv fr500 fr400

        .include "testutils.inc"

        start

        .global mp_exception
mpx:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    0x0e0,gr7               ; address of exception handler
        set_bctrlr_0_0  gr7
        set_spr_immed   128,lcr
        set_spr_addr    ok1,lr
        set_psr_et      1
        set_gr_immed    0,gr5

        set_spr_immed   0,msr0
        set_fr_iimmed   0x1234,0x5678,fr10
        set_fr_iimmed   0x7ffe,0x7ffe,fr11
        set_fr_iimmed   0xffff,0xffff,fr12
        set_fr_iimmed   0x0002,0x0001,fr13
        mqaddhss        fr10,fr12,fr14
        test_fr_limmed  0x1233,0x5677,fr14
        test_fr_limmed  0x7fff,0x7fff,fr15
        test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
        mtrap                           ; generate interrupt
        test_gr_immed   1,gr5

        and_spr_immed   0xffffc000,msr0 ; Clear msr0 fields
        mcmpsh          fr10,fr11,fcc0  ; no exception
        test_spr_bits   0x7000,12,0,msr0; msr0.mtt is clear
        mtrap                           ; nop
        test_gr_immed   1,gr5

        pass

; exception handler
ok1:
        test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
        inc_gr_immed    1,gr5
        rett            0
        fail