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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [nfdivs.cgs] - Rev 407
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# frv testcase for nfdivs $FRi,$FRj,$FRk# mach: fr500 fr550 frv.include "testutils.inc"float_constantsstartload_float_constants.global nfdivsnfdivs:nfdivs fr0,fr28,fr1test_fr_fr fr1,fr0test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr4,fr28,fr1test_fr_fr fr1,fr4test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr8,fr28,fr1test_fr_fr fr1,fr8test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr12,fr28,fr1test_fr_fr fr1,fr12test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr28,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr28,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr24,fr28,fr1test_fr_fr fr1,fr24test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr28,fr28,fr1test_fr_fr fr1,fr28test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr32,fr28,fr1test_fr_fr fr1,fr32test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr36,fr28,fr1test_fr_fr fr1,fr36test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr40,fr28,fr1test_fr_fr fr1,fr40test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr44,fr28,fr1test_fr_fr fr1,fr44test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr48,fr28,fr1test_fr_fr fr1,fr48test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr52,fr28,fr1test_fr_fr fr1,fr52test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr0,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr4,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr8,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr12,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr24,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr28,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr32,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr36,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr40,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr44,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr48,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr16,fr52,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr0,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr4,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr8,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr12,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr24,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr28,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr32,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr36,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr40,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr44,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr48,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr20,fr52,fr1test_fr_fr fr1,fr16test_fr_fr fr1,fr20test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr8,fr28,fr1test_fr_fr fr1,fr8test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr28,fr8,fr1test_fr_fr fr1,fr8test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr40,fr32,fr1test_fr_fr fr1,fr36test_spr_immed 0,fner1test_spr_immed 0,fner0; try to cause exceptionsset_spr_immed 0,fner0set_spr_immed 0,fner1nfdivs fr48,fr20,fr1; test_fr_fr fr1,fr44test_spr_immed 2,fner1test_spr_immed 0,fner0set_spr_immed 0,fner0set_spr_immed 0,fner1nfdivs fr52,fr16,fr1; test_fr_fr fr1,fr44test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr56,fr28,fr1; test_fr_fr fr1,fr44test_spr_immed 0,fner1test_spr_immed 0,fner0nfdivs fr60,fr28,fr1; test_fr_fr fr1,fr44test_spr_immed 2,fner1test_spr_immed 0,fner0pass
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