OpenCores

URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [div.cgs] - Rev 24

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for div $dr,$sr
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global div
div:
        mvi_h_gr r4, 0x18000
        mvi_h_gr r5, 8

        div r4, r5

        test_h_gr r4, 0x3000

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.