OpenCores

URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [lock.cgs] - Rev 24

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for lock $dr,@$sr
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global lock
lock:
        mvaddr_h_gr r4, data_loc
        mvi_h_gr    r5, 0

        lock r5, @r4

        test_h_gr r5, 0x12345678

        ; There is no way to test the lock bit

        unlock r5, @r4  ; Unlock the processor

        pass

data_loc:
        .word 0x12345678

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.