OpenCores

URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [mvtc.cgs] - Rev 24

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for mvtc $sr,$dcr
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global mvtc
mvtc:
        mvi_h_condbit 0
        mvi_h_gr r4, 1

        mvtc r4, cr1
        bc ok

        fail
ok:
        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.