OpenCores

URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [rac.cgs] - Rev 450

Go to most recent revision | Compare with Previous | Blame | View Log

# m32r testcase for rac
# mach(): m32r m32rx

        .include "testutils.inc"

        start

        .global rac
rac:

        mvi_h_accum0 1, 0x4001
        rac
        test_h_accum0 2, 0x10000

        mvi_h_accum0 0x3fff, 0xffff4000
        rac
        test_h_accum0 0x7fff, 0xffff0000

        mvi_h_accum0 0xffff8000, 0
        rac
        test_h_accum0 0xffff8000, 0

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.