OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [frv/] [arch.c] - Rev 373

Go to most recent revision | Compare with Previous | Blame | View Log

/* Simulator support for frv.
 
THIS FILE IS MACHINE GENERATED WITH CGEN.
 
Copyright 1996-2010 Free Software Foundation, Inc.
 
This file is part of the GNU simulators.
 
   This file is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.
 
   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.
 
   You should have received a copy of the GNU General Public License along
   with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
*/
 
#include "sim-main.h"
#include "bfd.h"
 
const MACH *sim_machs[] =
{
#ifdef HAVE_CPU_FRVBF
  & frv_mach,
#endif
#ifdef HAVE_CPU_FRVBF
  & fr550_mach,
#endif
#ifdef HAVE_CPU_FRVBF
  & fr500_mach,
#endif
#ifdef HAVE_CPU_FRVBF
  & tomcat_mach,
#endif
#ifdef HAVE_CPU_FRVBF
  & fr400_mach,
#endif
#ifdef HAVE_CPU_FRVBF
  & fr450_mach,
#endif
#ifdef HAVE_CPU_FRVBF
  & simple_mach,
#endif
  0
};
 
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.