OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [m32c/] [ChangeLog] - Rev 227

Compare with Previous | Blame | View Log

2010-01-20  DJ Delorie  <dj@redhat.com>

        * m32c.opc (MATH_OP): When doing subtraction, also set carry if
        the result is zero.

2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

        * configure: Regenerate.

2009-08-22  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

        * config.in: Regenerate.
        * configure: Likewise.

        * configure: Regenerate.

2009-08-14  DJ Delorie  <dj@redhat.com>

        * configure.in: Check for sys/select.h, termios.h, sys/socket.h,
        netinet/in.h, and netinet/tcp.h.
        * configure: Regenerate.
        * config.in: Add those headers.
        * main.c: Check for them.
        (setup_tcp_console): Disable if no networking.
        (main): Note missing networking or termios.
        * mem.c: Check for those headers.
        (stdin_ready): Disable if no termios.
        (m32c_sim_restore_console): Disable if no termios.
        (mem_get_byte): Disable console input if no termios.
        
2009-01-06  Joel Sherrill <joel.sherrill@oarcorp.com>

        * r8c.opc, m32c.opc: Add parentheses to remove warnings.

2008-10-01  DJ Delorie  <dj@redhat.com>

        * int.c (trigger_peripheral_interrupt): Clear interrupt pending
        bit when peripheral interrupts are serviced.

2008-07-11  Hans-Peter Nilsson  <hp@axis.com>

        * configure: Regenerate to track ../common/common.m4 changes.
        * config.in: Ditto.

2008-06-16  DJ Delorie  <dj@redhat.com>

        * m32c.opc (BRK, GDBBRK): Remove debug logic.
        * main.c (main): Add option to set raw console.
        * mem.h (m32c_use_raw_console): Declare.
        * mem.c (m32c_sim_restore_console): Only restore console if it's
        been previously set.
        (m32c_use_raw_console): Define.
        (mem_get_byte): Set raw console if m32c_use_raw_console is set.

2008-06-06  Vladimir Prus  <vladimir@codesourcery.com>
            Daniel Jacobowitz  <dan@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>

        * configure: Regenerate.

2008-06-06  DJ Delorie  <dj@redhat.com>

        * Makefile.in: Add Timer A support.
        * cpu.h (m32c_opcode_pc): New.
        (in_gdb): New.
        * gdb-if.c (sim_open): Add Timer A support.  Support unbuffered
        console.
        * int.c (trigger_interrupt): Manage the U flag properly.
        (trigger_based_interrupt): Likewise.
        (trigger_fixed_interrupt): New.
        (trigger_peripheral_interrupt): New.
        * int.h (trigger_peripheral_interrupt): New.
        * m32c.opc: Use m32c_opcode_pc throughout, as needed.
        (decode_m32c): Detect jump-to-zero with traceback.
        (BRK): Try to do the right thing, keeping track of whether we're
        in gdb or not, and if the user has provided a handler or not.
        (GBRK): Alternate break opcode for gdb, in case the user's app
        needs to use BRK for itself.
        (BRK2): Implement.
        * main.c: Add Timer A support.  Support TCP-based console.
        (setup_tcp_console): New.
        (main): Add Timer A support.  Support TCP-based console.
        * mem.h (m32c_sim_restore_console): New.
        * mem.c: Add Timer A support.  Support TCP-based console.
        (mem_ptr): Enhance NULL pointer detection.
        (stdin_ready): New.
        (m32c_sim_restore_console): New.
        (mem_get_byte): Check for console input ready.
        (update_timer_a): New.
        * r8c.opc (SSTR): Use r0l, not r0h.
        (REIT): Fix return frame logic.
        * reg.c (print_flags): New.
        (trace_register_changes): Use it.
        (m32c_dump_all_registers): New.
        * timer_a.h: New.
        
        * load.c: Fix indentation.
        * trace.c: Fix indentation.
        * trace.h: Fix indentation.

2006-06-26  DJ Delorie  <dj@redhat.com>

        * r8c.opc (decode_r8c): Don't bother reading the destination
        before moving a constant into it.  Fix borrow comparison for SUB.

2006-06-13  Richard Earnshaw  <rearnsha@arm.com>

        * configure: Regenerated.

2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>

        * configure: Regenerated.

2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>

        * configure: Regenerated.

2006-03-13  DJ Delorie  <dj@redhat.com>

        * mem.c (mem_put_byte): Hook simulated UART to stdout.
        (mem_put_hi): Hook in simulated trace port.
        (mem_get_byte): Hook in simulated uart control port.
        * opc2c: Be more picky about matching special comments.
        * r8c.opc (shift_op): Limit shift counts to -16..16.
        (BMcnd): Map conditional codes.
        * reg.c (condition_true): Mask condition code to 4 bits.
        * syscalls.c: Include local syscall.h.
        * syscall.h: New, copied from libgloss.

2005-10-06  Jim Blandy  <jimb@redhat.com>

        Simulator for Renesas M32C and M16C, by DJ Delorie <dj@redhat.com>,
        with further work from Jim Blandy <jimb@redhat.com> and
        Kevin Buettner <kevinb@redhat.com>.
        
        * ChangeLog: New.
        * Makefile.in: New.
        * blinky.S: New.
        * config.in: New.
        * configure: New.
        * configure.in: New.
        * cpu.h: New.
        * gdb-if.c: New.
        * gloss.S: New.
        * int.c: New.
        * int.h: New.
        * load.c: New.
        * load.h: New.
        * m32c.opc: New.
        * main.c: New.
        * mem.c: New.
        * mem.h: New.
        * misc.c: New.
        * misc.h: New.
        * opc2c.c: New.
        * r8c.opc: New.
        * reg.c: New.
        * safe-fgets.c: New.
        * safe-fgets.h: New.
        * sample.S: New.
        * sample.ld: New.
        * sample2.c: New.
        * srcdest.c: New.
        * syscalls.c: New.
        * syscalls.h: New.
        * trace.c: New.
        * trace.h: New.


Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.