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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tinsr.cgs] - Rev 227

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# Intel(r) Wireless MMX(tm) technology testcase for TINSR
# mach: xscale
# as: -mcpu=xscale+iwmmxt

        .include "testutils.inc"

        start

        .global tinsr
tinsr:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.

        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0

        # Test Byte Wide Insertion
        
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff

        tmcrr      wr0, r0, r1

        tinsrb     wr0, r2, #3
        
        tmrrc      r0, r1, wr0
        
        test_h_gr  r0, 0xff345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x111111ff
        
        # Test Half Word Wide Insertion
        
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff

        tmcrr      wr0, r0, r1

        tinsrh     wr0, r2, #2
        
        tmrrc      r0, r1, wr0
        
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abc11ff
        test_h_gr  r2, 0x111111ff
        
        # Test Word Wide Insertion
        
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x111111ff

        tmcrr      wr0, r0, r1

        tinsrw     wr0, r2, #1
        
        tmrrc      r0, r1, wr0
        
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x111111ff
        test_h_gr  r2, 0x111111ff
        
        pass

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