URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tmiaxy.cgs] - Rev 227
Compare with Previous | Blame | View Log
# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy# mach: xscale# as: -mcpu=xscale+iwmmxt.include "testutils.inc"start.global tmiaXYtmiaXY:# Enable access to CoProcessors 0 & 1 before# we attempt these instructions.mvi_h_gr r1, 3mcr p15, 0, r1, cr15, cr1, 0# Test Bottom Bottom Multilply Accumulatemvi_h_gr r0, 0x11223344mvi_h_gr r1, 0x55667788mvi_h_gr r2, 0x12345678mvi_h_gr r3, 0x9abcdef0tmcrr wr0, r0, r1tmiaBB wr0, r2, r3tmrrc r0, r1, wr0test_h_gr r0, 0x05f753c4test_h_gr r1, 0x55667788test_h_gr r2, 0x12345678test_h_gr r3, 0x9abcdef0# Test Bottom Top Multilply Accumulatemvi_h_gr r0, 0x11223344mvi_h_gr r1, 0x55667788mvi_h_gr r2, 0x12345678mvi_h_gr r3, 0x9abcdef0tmcrr wr0, r0, r1tmiaBT wr0, r2, r3tmrrc r0, r1, wr0test_h_gr r0, 0xeeede364test_h_gr r1, 0x55667787test_h_gr r2, 0x12345678test_h_gr r3, 0x9abcdef0# Test Top Bottom Multilply Accumulatemvi_h_gr r0, 0x11223344mvi_h_gr r1, 0x55667788mvi_h_gr r2, 0x12345678mvi_h_gr r3, 0x9abcdef0tmcrr wr0, r0, r1tmiaTB wr0, r2, r3tmrrc r0, r1, wr0test_h_gr r0, 0x0ec85c04test_h_gr r1, 0x55667788test_h_gr r2, 0x12345678test_h_gr r3, 0x9abcdef0# Test Top Top Multilply Accumulatemvi_h_gr r0, 0x11223344mvi_h_gr r1, 0x55667788mvi_h_gr r2, 0x12345678mvi_h_gr r3, 0x9abcdef0tmcrr wr0, r0, r1tmiaTT wr0, r2, r3tmrrc r0, r1, wr0test_h_gr r0, 0x09eed974test_h_gr r1, 0x55667788test_h_gr r2, 0x12345678test_h_gr r3, 0x9abcdef0pass